Source drive chip having a power supply circuit and display apparatus
A source drive include a power supply circuit that includes a charge pump, a reference source generation circuit, and a low-dropout (LDO) regulator. The charge pump includes at least two on-chip capacitors, is coupled to the reference source generation circuit, and is configured to provide a negative voltage level for the reference source generation circuit based on an external positive voltage power supply. The reference source generation circuit is coupled to the LDO regulator. The reference source generation circuit is configured to provide a reference voltage for the LDO regulator based on the negative voltage level. The LDO regulator is coupled to a load circuit, and the LDO regulator is configured to output a power supply voltage to the load circuit based on the reference voltage and an external negative voltage power supply.
1 . A source drive chip, comprising:
a load circuit; and
a power supply circuit comprising:
a charge pump configured to provide a negative voltage level based on an external positive voltage power supply and comprising:
a first switch;
a second switch;
a third switch;
a fourth switch;
a first on-chip capacitor comprising:
a first end configured to couple through the first switch to the external positive voltage power supply; and
a second end coupled by the third switch to a ground; and
a second on-chip capacitor comprising:
a third end coupled in series to the second switch and to the ground; and
a fourth end coupled in series with the fourth switch and configured to provide the negative voltage level to the reference source generation circuit;
a reference source generation circuit coupled with the charge pump and configured to provide a reference voltage based on the negative voltage level; and
a low-dropout (LDO) regulator coupled to the load circuit and to the reference source generation circuit and configured to output a power supply voltage to the load circuit based on the reference voltage and an external negative voltage power supply.
2 . The source drive chip of claim 1 , wherein a capacitance value of each of the two on-chip capacitors is less than 10 nanofarads (nF).
3 . The source drive chip of claim 1 , wherein the LDO regulator comprises:
an operational amplifier comprising:
a positive input configured to receive the reference voltage;
a negative input configured to receive a feedback voltage;
a negative voltage power supply end configured to couple to the external negative voltage power supply;
a positive voltage power supply end connection to a ground; and
an output end;
a power output transistor comprising:
a gate coupled to the output end;
a source configured to couple to the external negative voltage power supply; and
a drain configured to provide the power supply voltage;
a first feedback resistor;
a second feedback resistor coupled in series with the first feedback resistor, wherein the first feedback resistor and the second feedback resistor are configured to couple the drain to the ground;
a series connection point between the first feedback resistor and the second feedback resistor configured to output the feedback voltage; and
an output capacitor comprising:
a fifth end coupled to the drain; and
a sixth end configured to couple to the ground.
4 . The source drive chip of claim 3 , wherein the operational amplifier is a folded cascode operational amplifier configured to separately adjust decoupling of an input stage transconductance and an output impedance.
5 . The source drive chip of claim 3 , wherein the first feedback resistor and the second feedback resistor are polycrystalline silicon resistors.
6 . The source drive chip of claim 1 , wherein the reference source generation circuit is a reference voltage circuit.
7 . The source drive chip of claim 1 , wherein the load circuit comprises a plurality of medium-voltage components, and wherein a withstand voltage of the medium-voltage component is not greater than 8 volts (V).
8 . The source drive chip of claim 1 , wherein the load circuit is an on-screen initialization voltage power supply system.
9 . The source drive chip of claim 1 , wherein the power supply voltage is a negative voltage greater than a voltage of the external negative voltage power supply.
10 . The source drive chip of claim 1 , wherein the power supply voltage is a not less than negative 6 volts (V).
11 . A display apparatus, comprising:
a display panel; and
a power supply circuit comprising:
a charge pump configured to provide a negative voltage level based on an external positive voltage power supply and comprising:
a first switch;
a second switch;
a third switch;
a fourth switch;
a first on-chip capacitor comprising:
a first end configured to couple through the first switch to the external positive voltage power supply; and
a second end coupled by the third switch to a ground; and
a second on-chip capacitor comprising:
a third end coupled in series to the second switch and to the ground; and
a fourth end coupled in series with the fourth switch and configured to provide the negative voltage level to the reference source generation circuit;
a reference source generation circuit coupled with the charge pump and configured to provide a reference voltage based on the negative voltage level; and
a low-dropout (LDO) regulator coupled to the load circuit and to the reference source generation circuit and configured to output a power supply voltage to the load circuit based on the reference voltage and an external negative voltage power supply.
12 . The display apparatus of claim 11 , wherein the display panel comprises organic light emitting diode (OLED) display.
13 . The display apparatus of claim 11 , wherein a capacitance value of each of the two on-chip capacitors is less than 10 nanofarads (nF).
14 . The display apparatus of claim 11 , wherein the LDO regulator comprises:
an operational amplifier comprising:
a positive input configured to receive the reference voltage;
a negative input configured to receive a feedback voltage;
a negative voltage power supply end configured to couple to the external negative voltage power supply;
a positive voltage power supply end connection to ground; and
an output end;
a power output transistor comprising:
a gate coupled to the output end;
a source configured to couple to the external negative voltage power supply; and
a drain configured to provide the power supply voltage;
a first feedback resistor;
a second feedback resistor coupled in series with the first feedback resistor, wherein the first feedback resistor and the second feedback resistor are configured to couple the drain to the ground;
a series connection point between the first feedback resistor and the second feedback resistor configured to output the feedback voltage; and
an output capacitor comprising:
a fifth end coupled to the drain; and
a sixth end configured to couple to the ground.
15 . The display apparatus of claim 14 , wherein the operational amplifier is a folded cascode operational amplifier configured to separately adjust decoupling of input stage transconductance and an output impedance.
16 . The display apparatus of claim 14 , wherein the first feedback resistor and the second feedback resistor are polycrystalline silicon resistors.
17 . The display apparatus of claim 11 , wherein the reference source generation circuit is a reference voltage circuit.
18 . The display apparatus of claim 11 , wherein the display panel comprises a plurality of medium-voltage components, and a withstand voltage of the medium-voltage component is not greater than 8 volts (V).
19 . The display apparatus of claim 11 , wherein the display panel comprises an on-screen initialization voltage power supply system.
20 . The display apparatus of claim 11 , wherein the power supply voltage is a negative voltage greater than a voltage of the external negative voltage power supply.