Circuit and method for power management

1 . A circuit, comprising:

a memory circuit; and

a power management circuit comprising a first circuit, wherein

the first circuit is configured to,

in response to a first state of a first power management control signal and a first state of a second power management control signal,

control supply of a first supply voltage to the memory circuit in accordance with a first power mode control signal,

in response to a second state of the first power management control signal,

store a state of the first power mode control signal, and

control supply of the first supply voltage to the memory circuit in accordance with the stored state of the first power mode control signal, and

the power management circuit is configured to,

in response to a second state of the second power management control signal,

disable a part of the first circuit.

2 . The circuit of claim 1 , wherein

the first circuit is configured to store the state of the first power mode control signal in response to the second state of the first power management control signal before said part of the first circuit being disabled in response to the second state of the second power management control signal.

3 . The circuit of claim 1 , wherein

the first circuit comprises:

a first level shifter circuit configured to generate a first level-shifted signal corresponding to the first power mode control signal, to control supply of the first supply voltage to the memory circuit,

the power management circuit further comprises:

a second level shifter circuit configured to generate a second level-shifted signal corresponding to the first power mode control signal, to control supply of a second supply voltage to the memory circuit, and

the power management circuit is configured to, in response to the second state of the second power management control signal, disable the first level shifter circuit and the second level shifter circuit.

4 . The circuit of claim 3 , wherein

the first circuit further comprises a latch circuit configured to generate a latch output signal to control supply of the first supply voltage to the memory circuit, based on

the first level-shifted signal, and

the first power management control signal.

5 . The circuit of claim 3 , wherein

the power management circuit further comprises a logic circuit configured to generate a combined power mode control signal based on

the first power mode control signal, and

a second power mode control signal,

the power management circuit is configured to, based on the combined power mode control signal, control supply of a third supply voltage to the memory circuit, and

the second level shifter circuit is configured to, based on the combined power mode control signal, generate the second level-shifted signal to control supply of the second supply voltage to the memory circuit.

6 . The circuit of claim 3 , wherein

the power management circuit is further configured to, in response to the second state of the second power management control signal, set the first level-shifted signal and the second level-shifted signal to a predetermined voltage.

7 . A circuit, comprising: a memory circuit and a power management circuit, wherein the power management circuit comprises:

a first input configured to receive a first power management control signal;

a second input configured to receive a second power management control signal;

a third input configured to receive a first power mode control signal;

a first level shifter circuit having:

an input coupled to the third input, and

an output;

a latch circuit having:

a control input coupled to the first input,

a data input coupled to the output of the first level shifter circuit, and

an output configured to control supply of a first supply voltage to external circuitry;

a second level shifter circuit having:

an input coupled to the third input, and

an output configured to control supply of a second supply voltage to the external circuitry; and

a first header circuit having a control input coupled to the second input, the first header circuit coupled between

a first node of a first power supply voltage, and

at least one of the first level shifter circuit or the second level shifter circuit.

8 . The circuit of claim 7 , the power management circuit further comprising:

a switch having a control input coupled to the second input, the switch coupled between

a reference node of a reference voltage, and

the output of the first level shifter circuit or the second level shifter circuit.

9 . The circuit of claim 7 , the power management circuit further comprising:

a first switch having a control input coupled to the second input, the first switch coupled between

a reference node of a reference voltage, and

the output of the first level shifter circuit; and

a second switch having a control input coupled to the second input, the second switch coupled between

the reference node of the reference voltage, and

the output of the second level shifter circuit.

10 . The circuit of claim 7 , the power management circuit further comprising:

a fourth input configured to receive a second power mode control signal; and

a logic circuit having:

inputs correspondingly coupled to the third input and the fourth input, and

an output configured to control supply of a third supply voltage to the external circuitry.

11 . The circuit of claim 10 , wherein

the output of the logic circuit is coupled to the input of the second level shifter circuit.

12 . The circuit of claim 7 , the power management circuit further comprising:

at least one circuit coupled to a second node of a second power supply voltage different from the first power supply voltage; and

a second header circuit coupled to the second node, and configured to controllably disconnect the second power supply voltage from the second node.

13 . The circuit of claim 12 , wherein

the at least one circuit comprises at least one of:

a first connection circuit coupled between the third input and the input of the first level shifter circuit,

a second connection circuit coupled between the third input and the input of the second level shifter circuit, or

an output header circuit configured to controllably supply a third supply voltage to the memory circuit, the third supply voltage corresponding to the second power supply voltage.

14 . A circuit, comprising: a memory circuit and a power management circuit, wherein the power management circuit is configured to:

output a first supply voltage to a memory array of the memory circuit, the first supply voltage corresponding to a first power supply voltage and

output a second supply voltage to a peripheral circuit of the memory circuit, the second supply voltage corresponding to a second power supply voltage different from the first power supply voltage,

in response to at least one of a first power mode control signal or a second power mode control signal, stop outputting the second supply voltage,

store a state of the first power mode control signal, and

after storing the state of the first power mode control signal,

disconnect the first power supply voltage from at least one circuit of the power management circuit, and

turn OFF the second power supply voltage.

15 . The circuit of claim 14 , wherein the power management circuit is further configured to:

output a third supply voltage to the peripheral circuit, the third supply voltage corresponding to the first power supply voltage, and

in response to the at least one of the first power mode control signal or the second power mode control signal, stop outputting the third supply voltage.

16 . The circuit of claim 15 , wherein the power management circuit is further configured to:

disconnect the first power supply voltage from at least one interface circuit in the peripheral circuit, the at least one interface circuit interfacing between a first power domain of the first power supply voltage and a second power domain of the second power supply voltage.

17 . The circuit of claim 14 , wherein the power management circuit is further configured to:

in response to the stored state of the first power mode control signal corresponding to a first state, stop outputting the first supply voltage, and

in response to the stored state of the first power mode control signal corresponding to a second state different from the first state, continue outputting the first supply voltage.

18 . The circuit of claim 17 , wherein

the first state corresponds to a first power mode of the memory circuit, and

the power management circuit is configured to stop outputting the second supply voltage in response to the first power mode control signal.

19 . The circuit of claim 18 , wherein

the second state corresponds to a second power mode of the memory circuit, the second power mode having higher power consumption than the first power mode, and

the power management circuit is configured to stop outputting the second supply voltage in response to the second power mode control signal.

20 . The circuit of claim 14 , wherein the power management circuit is further configured to:

turn ON the second power supply voltage, and

after turning ON the second power supply voltage,

reconnect the first power supply voltage to the at least one circuit of the power management circuit, and

resume outputting the first supply voltage and the second supply voltage.