Compact data latches
Technology for compact data latches. Two global driver transistors are each connected to a large number of compact data latches. The global driver transistors may be operated during a simultaneous latch operation in each of the compact data latches. A latch operation may discharge a high voltage from a latch output, depending on whether that output is to go from the high voltage to a low voltage. Such discharge could lead to a shoot through voltage and/or fight between a PMOS and an NMOS transistor in the data latch. Turning off one of the global driver transistors during a latch operation prevents shoot through current and also prevents a fight between a PMOS and an NMOS transistor in the data latch. The global driver transistors occupy a small chip area.
1 . An apparatus comprising:
a plurality of data latches, each data latch comprising:
a first inverter having a first transistor, a second transistor, and a first output between the first transistor and the second transistor, the first transistor having a first terminal connected to the first output, the first transistor having second terminal, the second transistor having a first terminal connected to the first output, the second transistor having a second terminal; and
a second inverter having a third transistor, a fourth transistor, and a second output between the third transistor and the fourth transistor, the third transistor having a first terminal connected to the second output, the third transistor having a second terminal, the fourth transistor having a first terminal connected to the second output, the fourth transistor having a second terminal, wherein the first inverter and the second inverter are cross-coupled with gate terminals of the first transistor and the second transistor connected to the second output and gate terminals of the third transistor and the fourth transistor connected to the first output;
a single first global driver transistor coupled to the second terminal of the first transistor in each data latch of the plurality of data latches, the single first global driver transistor configured to receive and selectively pass a first data state voltage to the second terminal of each first transistor, the first data state voltage being higher than a second data state voltage; and
a single second global driver transistor coupled to the second terminal of the third transistor in each data latch of the plurality of data latches, the single second global driver transistor configured to receive and selectively pass the first data state voltage to the second terminal of each third transistor.
2 . The apparatus of claim 1 , further comprising a control circuit in communication with the plurality of data latches, the first global driver transistor, and the second global driver transistor, the control circuit configured to maintain the first global driver transistor in an on state during a simultaneous latch operation in each of the data latches to selectively provide the first data state voltage to the second terminal of the first transistor in each data latch of the plurality of data latches and to turn off the second global driver transistor during the latch operation to selectively disconnect the second terminal of the third transistor in each data latch of the plurality of data latches from the first data state voltage in each of the data latches, wherein the latch operation discharges the first data state voltage from the second output of at least a subset of the plurality of data latches.
3 . The apparatus of claim 2 , wherein the latch operation in each of the data latches is a first data latch operation, the subset of the plurality of data latches is a first subset, and the control circuit is further configured to maintain the second global driver transistor in an on state during a second simultaneous latch operation in each of the data latches to selectively provide the first data state voltage to the second terminal of the third transistor in each data latch of the plurality of data latches and to turn the first global driver transistor off during the second simultaneous latch operation to selectively disconnect the second terminal of the first transistor in each data latch of the plurality of data latches from the first data state voltage, wherein the second latch operation discharges the first data state voltage from the first output of at least a second subset of the plurality of data latches.
4 . The apparatus of claim 3 , further comprising:
a plurality comparison circuits, each comparison circuit configured to connect to and sense a condition of a selected non-volatile memory cell, each comparison circuit associated with a data latch of the plurality of data latches.
5 . The apparatus of claim 4 , wherein to perform the latch operation the control circuit is further configured to:
for each selected non-volatile memory sell, latch a voltage from the comparison circuit sensing the condition the selected non-volatile memory cell into the data latch associated with the comparison circuit.
6 . The apparatus of claim 5 , wherein to perform the latch operation the control circuit is further configured to:
latch a respective bit value into each data latch of the plurality of data latches; and
program the bit value from each respective data latch into the selected non-volatile memory cell associated with the data latch.
7 . The apparatus of claim 2 , wherein:
each data latch further comprises:
a first access transistor coupled between the first output and a local data bus; and
a second access transistor coupled between the second output and the local data bus; and
the control circuit is further configured to:
provide the second data state voltage on the local data bus of a subset of the plurality of data latches that have the first data state voltage at the second output; and
turn on the second access transistor to connect the second output to the local data bus while the first global driver transistor is on and while the second global driver transistor is off, wherein the first data state voltage on the second output is discharged to the local data bus thereby resulting in the second data state voltage on the second output.
8 . The apparatus of claim 7 , wherein the control circuit is configured to provide the second data state voltage on the local data bus in a latch reset operation.
9 . The apparatus of claim 7 , wherein the control circuit is configured to provide the second data state voltage on the local data bus of the subset of the plurality of data latches by connecting respective outputs of a different set of data latches to the local data bus of the subset of the plurality in a data exchange operation.
10 . The apparatus of claim 7 , wherein the control circuit is further configured to:
maintain the first access transistor in an off state while the second access transistor and the first global driver transistor are on, wherein the first transistor of the first inverter charges the first output using the voltage from the first global driver transistor when the first transistor is on as a result of discharging the voltage from the second output to the local data bus.
11 . The apparatus of claim 1 , further comprising:
a first electrical line connecting the first global driver transistor to the second terminal of the first transistor in each data latch of the plurality of data latches; and
a first plurality of capacitors connected to the first electrical line.
12 . The apparatus of claim 11 , further comprising:
a second electrical line connecting the second global driver transistor to the second terminal of the third transistor in each data latch of the plurality of data latches; and
a second plurality of capacitors connected to the second electrical line.
13 . The apparatus of claim 12 , wherein:
the first plurality of capacitors are located at regular intervals along the first electrical line; and
the second plurality of capacitors are located at regular intervals along the second electrical line.
14 . The apparatus of claim 1 , wherein:
the first transistor of the first inverter comprises a PMOS transistor;
the second transistor of the first inverter comprises an NMOS transistor;
the third transistor of the second inverter comprises a PMOS transistor;
the fourth transistor of the second inverter comprises an NMOS transistor; and
each data latch further comprises:
a first access transistor coupled between the first output and a local data bus; and
a second access transistor coupled between the second output and the local data bus.
15 . A method for operating data latches, the method comprising:
providing a first data state voltage to a local data bus in each of a plurality of read/write circuits, each read/write circuit having a sense amplifier and having a data latch having a cross-coupled CMOS inverter pair, the cross-coupled CMOS inverter pair having a first PMOS transistor connected to a first latch output and a second PMOS transistor connected to a second latch output, wherein the first latch output of a first set of the data latches has a first data state voltage and the first latch output of a second set of the data latches has a second data state voltage that is greater than the first data state voltage;
maintaining a first global driver transistor in an on state during a simultaneous latch operation in each of the data latches to selectively provide the second data state voltage to a source terminal of the second PMOS transistor in each data latch and turning off a second global driver transistor during the simultaneous latch operation to selectively disconnect a source terminal of the first PMOS transistor in each data latch from the second data state voltage; and
connecting the first latch output of each data latch to the local data bus in each respective read/write circuit while maintaining the first global driver transistor in the on state and keeping the second global driver transistor off, thereby discharging the second data state voltage at the first latch output of the second first set of the data latches to the local data bus and charging the second latch output of the first set of the data latches to the second data state voltage.
16 . The method of claim 15 , further comprising:
providing a low voltage to a low voltage node connected to a first NMOS transistor of each data latch and to a second NMOS transistor of each data latch, the first NMOS transistor, the second NMOS transistor, the first PMOS transistor, and the second PMOS transistor comprising a cross-coupled CMOS inverter pair, the low voltage being lower than the second data state voltage, the low voltage provided to the low voltage node while discharging the first latch output of each data latch in the second set to the first data state voltage and charging the second latch output of each data latch in the first set to the second data state voltage.
17 . A non-volatile storge system, comprising:
a plurality of read/write circuits, each read/write circuit having a comparison circuit, a local data bus, and a first data latch connected to the local data bus, each comparison circuit configured to connect to and sense a condition of a selected non-volatile memory cell, the first data latch in each read/write circuit comprising:
a first CMOS inverter and a second CMOS inverter that are cross-coupled, the first CMOS inverter having a first NMOS transistor coupled to a low voltage node and a first PMOS transistor having a first terminal, the first CMOS inverter having a first output at a first node between the first NMOS transistor and the first PMOS transistor, the second CMOS inverter having a second NMOS transistor coupled to the low voltage node and a second PMOS transistor having a second terminal, the second CMOS inverter having a second output at a second node between the second NMOS transistor and the second PMOS transistor;
a first access transistor coupled between the first output and the local data bus of the read/write circuit; and
a second access transistor coupled between the second output and the local data bus of the read/write circuit;
a first global driver transistor;
a first electrical line connecting the first global driver transistor to the first terminal of the first PMOS transistor in the first data latch in each read/write circuit, wherein the first global driver transistor is configured to selectively provide a first voltage to the first terminal of the first PMOS transistor;
a first plurality of capacitors connected to the first electrical line;
a second global driver transistor;
a second electrical line connecting the second global driver transistor to the second terminal of the second PMOS transistor in the first data latch in each read/write circuit, wherein the second global driver transistor is configured to selectively provide a second voltage to the second terminal of the second PMOS transistor; and
a second plurality of capacitors connected to the second electrical line.
18 . The non-volatile storge system of claim 17 , wherein:
the first plurality of capacitors are located at regular intervals along the first electrical line; and
the second plurality of capacitors are located at regular intervals along the second electrical line.