Low power intermediate pre-charge operations in memory
View Patent ↗Memory devices, circuits, and a method of operating the same are disclosed. In one aspect, a memory device includes a memory cell coupled between a first bit line and a second bit line. The memory cell includes a write circuit configured to write data to the memory cell via the first bit line and the second bit line during a write operation. The memory cell includes a voltage equalizing device configured to equalize the voltage of the first bit line and the second bit line following the write operation and prior to a second memory operation for the memory cell.
1 . A memory device, comprising:
a memory cell coupled between a first bit line and a second bit line;
a write circuit configured to write data to the memory cell via the first bit line and the second bit line during a write operation;
a first transistor coupled to the first bit line and gated by a write clock signal;
a second transistor coupled between the first transistor and a supply voltage, the second transistor having a diode-connected configuration; and
a voltage equalizing device configured to equalize a voltage of the first bit line and the second bit line following the write operation and prior to a read operation for the memory cell.
2 . The memory device of claim 1 , wherein the voltage equalizing device is further configured to set the voltage of the first bit line and the second bit line to a voltage less than the supply voltage.
3 . The memory device of claim 1 , wherein the voltage equalizing device equalizes the voltage of the first bit line and the second bit line during a double pump operation.
4 . The memory device of claim 1 , wherein the write circuit comprises at least one NOR gate and at least one NAND gate.
5 . The memory device of claim 1 , wherein the voltage equalizing device comprises at least one p-type device.
6 . The memory device of claim 5 , wherein the voltage equalizing device further comprises at least one n-type device coupled to the at least one p-type device in parallel.
7 . The memory device of claim 1 , further comprising at least one pre-charge device coupled to the first bit line and the second bit line.
8 . The memory device of claim 7 , wherein the at least one pre-charge device is coupled to the voltage equalizing device.
9 . The memory device of claim 1 , further comprising at least one voltage clamping device coupled to the second bit line.
10 . The memory device of claim 9 , wherein the at least one voltage clamping device is further configured to clamp the voltage of the first bit line or the second bit line according to a control signal.
11 . A memory circuit, comprising:
a first bit line and a second bit line coupled to a memory cell;
a first transistor in parallel with the memory cell, a first source/drain terminal of the first transistor coupled to the first bit line, a second source/drain terminal of the first transistor coupled to the second bit line, and a gate terminal of the first transistor receiving a voltage equalization signal configured to equalize a voltage of the first bit line and the second bit line between memory operations; and
a second transistor and a third transistor, wherein a first source/drain terminal of the second transistor is coupled to a supply voltage, a second source/drain terminal of the second transistor coupled to a first source/drain terminal of the third transistor, and a second source/drain terminal of the third transistor coupled to the first bit line, and wherein the third transistor is gated by a write clock signal.
12 . The memory circuit of claim 11 , further comprising a fourth transistor and a fifth transistor, the fourth transistor coupled to the supply voltage and the first bit line, the fifth transistor coupled to the supply voltage and the second bit line, each of the fourth transistor and the fifth transistor receiving a pre-charge signal.
13 . The memory circuit of claim 11 , further comprising a second transistor in parallel with the first transistor.
14 . The memory circuit of claim 11 , wherein the first transistor is a p-type transistor.
15 . The memory circuit of claim 11 , wherein a gate terminal of the second transistor is coupled to the second source/drain terminal of the second transistor.
16 . The memory circuit of claim 11 , wherein a gate terminal of the second transistor receives a voltage clamp control signal.
17 . A method, comprising:
pre-charging a first bit line and a second bit line coupled to a memory cell;
performing a first memory operation for the memory cell, wherein a voltage of at least the first bit line is clamped during the first memory operation, the voltage being clamped using (i) a first transistor coupled to the first bit line and gated by a write clock signal, and (ii) a second transistor coupled between the first transistor and a supply voltage, the second transistor having a diode-connected configuration;
equalizing a voltage of the first bit line and the second bit line of the memory cell following the first memory operation and prior to a second memory operation; and
performing the second memory operation for the memory cell following equalization of the voltage of the first bit line and the second bit line.
18 . The method of claim 17 , wherein the voltage of the first bit line and the second bit line is equalized to a voltage less than a supply voltage.
19 . The method of claim 17 , wherein the first memory operation is a read operation and the second memory operation is a write operation.
20 . The method of claim 19 , wherein the write clock signal is in a logic high state during the read operation and in a logic low state during the write operation.