Adjustable delay propagation of a control signal to different page buffer driver groups
A microelectronic device comprises a microelectronic device structure comprising a section comprising page buffers, and an additional section horizontally neighboring the section and comprising page buffer drivers and a timing delay chain coupled to the page buffer drivers. Each of the page buffer drivers is coupled to a different group of the page buffers than each other of the page buffer drivers. The timing delay chain comprises timing delay circuits coupled in series with one another. Each of the timing delay circuits is configured to adjustably delay propagation of a control signal therethrough. Memory devices, methods of operating memory devices, and electronic systems are also described.
1 . A method of operating a memory device, comprising delaying propagation of a control signal to different page buffer drivers coupled to different groups of page buffers operatively associated with at least one plane of memory cells to stagger control of the different groups of page buffers in time, delaying propagation of the control signal including adjustably delaying propagation of the control signal through a series of timing delay stages coupled to the different page buffer drivers, each of the timing delay stages coupled in series with one another and individually configured to adjustably delay propagation of the control signal to a respective one of the different page buffer drivers.
2 . The method of claim 1 , wherein:
the different groups of page buffers are confined within one plane section of a base structure, the one plane section of the base structure operatively associated with only one plane of the memory cells; and
delaying propagation of the control signal to the different page buffer drivers comprises asynchronously controlling the different groups of page buffers confined within the one plane section of the base structure.
3 . The method of claim 1 , wherein:
at least some of the different groups of page buffers are confined within different plane sections of a base structure than one another, the different plane sections of the base structure operatively associated with different planes of the memory cells than one another; and
delaying propagation of the control signal to the different page buffer drivers comprises asynchronously controlling first groups of page buffers within at least one of the different plane sections relative to second groups of page buffers within at least one other of the different plane sections.
4 . The method of claim 3 , wherein asynchronously controlling first groups of page buffers within at least one of the different plane sections relative to second groups of page buffers within at least one other of the different plane sections comprises:
simultaneously controlling two or more of the first groups of page buffers within two or more of the different plane sections, each of the two or more of the first groups of page buffers within a different one of the two or more of the different plane sections than each other of the two or more of the first groups of page buffers; and
simultaneously controlling two or more of the second groups of page buffers within two or more other of the different plane sections, each of the two or more of the second groups of page buffers within a different one of the two or more other of the different plane sections than each other of the two or more of the second groups of page buffers.
5 . The method of claim 1 , wherein adjustably delaying propagation of the control signal through the series of timing delay stages comprises staggering transitions in logic levels of the control signal by way of the series of timing delay stages to delay propagation of the control signal to page buffer drivers positioned progressively farther along the series of timing delay stages relative to preceding page buffer drivers.
6 . The method of claim 1 , wherein each of the timing delay stages comprises a trimmable discharge circuit configured to adjust a delay in propagating the control signal therethrough.
7 . The method of claim 6 , wherein the trimmable discharge circuit comprises a plurality of nMOSFETs electrically connected in parallel, and wherein adjustably delaying propagation of the control signal comprises selectively activating individual ones of the nMOSFETs to control a current strength of a discharge path.
8 . The method of claim 7 , wherein increasing a quantity of the nMOSFETs that are activated increases the current strength of the discharge path and reduces the delay in propagating the control signal through a respective one of the timing delay stages.
9 . The method of claim 6 , wherein each of the timing delay stages further comprises:
a first inversion sub-stage comprising a first inverting buffer;
a second inversion sub-stage comprising a CMOS inverter, the trimmable discharge circuit, and a capacitor, a voltage input terminal of the CMOS inverter coupled to an output terminal of the first inverting buffer, a source terminal of a pMOSFET of the CMOS inverter coupled to a supply voltage line, the trimmable discharge circuit coupled to a source terminal of an nMOSFET of the CMOS inverter and to ground, and the capacitor coupled to a voltage output terminal of the CMOS inverter; and
a third inversion sub-stage comprising a second inverting buffer having an input terminal coupled to the voltage output terminal of the CMOS inverter.
10 . The method of claim 1 , further comprising propagating the control signal through inverters interposed between and in series with the timing delay stages.
11 . The method of claim 10 , wherein an output terminal of each of the timing delay stages is coupled to an input terminal of one of the inverters and an input terminal of a respective one of the different page buffer drivers, and an output terminal of each of the inverters is coupled to an input terminal of a subsequent one of the timing delay stages.
12 . The method of claim 1 , wherein each of the different page buffer drivers drives a respective one of the different groups of page buffers by way of a conductive line extending through a plane section of the base structure comprising the different groups of page buffers.
13 . The method of claim 1 , wherein adjustably delaying propagation of the control signal through each of the timing delay stages comprises delaying propagation of the control signal by at least 10 nanoseconds per timing delay stage.
14 . The method of claim 1 , wherein a quantity of the timing delay stages equals a quantity of the different page buffer drivers.
15 . A method of operating a memory device, comprising:
receiving a control signal at a timing delay chain comprising a series of timing delay circuits coupled in series with one another, each of the timing delay circuits configured to adjustably delay propagation of the control signal therethrough;
propagating the control signal through the series of timing delay circuits to asynchronously deliver the control signal to different page buffer drivers coupled to different groups of page buffers; and
driving, by each of the different page buffer drivers responsive to receiving the control signal, a respective one of the different groups of page buffers by way of conductive lines extending through a plane section of a base structure of the memory device.
16 . The method of claim 15 , wherein propagating the control signal through the series of timing delay circuits comprises adjusting a delay of each of the timing delay circuits by selectively activating nMOSFETs of a trimmable discharge circuit within each of the timing delay circuits.
17 . The method of claim 15 , wherein the different groups of page buffers each comprise sense amplifiers within sense amplifier sub-regions of a plane section, each of the conductive lines coupling one of the different page buffer drivers to the sense amplifiers within two or more of the sense amplifier sub-regions located within different sense amplifier regions of the plane section.
18 . The method of claim 15 , further comprising serializing a page buffer elaboration phase across different plane sections of the base structure, control of page buffers within at least one of the different plane sections staggered in time relative to control of page buffers within at least one other of the different plane sections.
19 . A method of operating a memory device, comprising:
adjustably delaying propagation of a control signal through each of a series of timing delay stages to stagger delivery of the control signal to different page buffer drivers, each of the timing delay stages comprising a trimmable discharge circuit comprising a plurality of nMOSFETs electrically connected in parallel, selective activation of individual ones of the nMOSFETs adjusting a delay of a respective timing delay stage; and
asynchronously driving, by the different page buffer drivers responsive to the staggered delivery of the control signal, different groups of page buffers operatively associated with at least one plane of memory cells of the memory device.
20 . The method of claim 19 , wherein each of the timing delay stages further comprises a CMOS inverter and a capacitor, and wherein the trimmable discharge circuit is coupled between a source terminal of an nMOSFET of the CMOS inverter and ground, the capacitor coupled to a voltage output terminal of the CMOS inverter, a current strength of a discharge path for discharging the capacitor determined by a quantity of the nMOSFETs of the trimmable discharge circuit that are activated.