Memory subarray and interconnection circuit arrangement
Methods, systems, and devices for memory array circuit arrangement are described. A memory device may include a memory subarray, which may include a complementary metal oxide semiconductor (CMOS) circuitry under array (CuA) circuitry area and a word line driver region (e.g., word line driver circuitry) or a digit line driver region (e.g., digit line driver circuitry, sense amplifier circuitry multiplexed with the digit line driver circuitry). The memory subarray may include a first interconnect extending in a first and traversing at least a first portion of the CuA circuitry area of the memory subarray. The first interconnect may be coupled with the first portion of the CuA circuitry area and a first interconnection layer. Additionally, each memory subarray may include a second interconnect extending in a second direction and traversing at least a second portion of the CuA circuitry area of the memory subarray.
1 . An apparatus, comprising:
an array of memory cells comprising a subarray, wherein the subarray comprises:
a first interconnect extending in a first direction and traversing at least a first portion of a first substrate of the subarray, the first interconnect coupled with the first portion of the first substrate and a first interconnection layer, wherein the first interconnect is a socket feed-through region that does not electrically contact any word line or digit line; and
a second interconnect extending in a second direction and traversing at least a second portion of the first substrate of the subarray, the second interconnect coupled with the second portion of the first substrate and the first interconnection layer, wherein the second interconnect is a socket feed-through region that does not electrically contact any word line or digit line and the first portion and the second portion of the first substrate comprise at least a first edge and a second edge of the first substrate, respectively, and wherein the first substrate comprises complementary metal-oxide-semiconductor circuitry under arrays (CuA) that is adjacent to the first edge and the second edge.
2 . The apparatus of claim 1 , further comprising:
a first driver extending in the second direction; or
a second driver extending in the first direction.
3 . The apparatus of claim 2 , wherein:
the array of memory cells comprises a plurality of subarrays, the plurality of subarrays comprising a first group of subarrays; and
the first group of subarrays comprising the subarray, a second subarray adjacent to the subarray, a third subarray adjacent to the subarray, and a fourth subarray adjacent to the second subarray and the third subarray.
4 . The apparatus of claim 3 , wherein each subarray of the first group of subarrays comprises a respective substrate, the respective substrate combined to form a single substrate that comprises the first substrate.
5 . The apparatus of claim 3 , wherein:
the subarray comprises a first portion of the first driver associated with a first subset of word lines of the array of memory cells;
the third subarray comprises a second portion of the first driver associated with a second subset of word lines of the array of memory cells different from the first subset of word lines;
the second subarray comprises a first portion of the second driver associated with a first subset of digit lines of the array of memory cells; and
the fourth subarray comprises a second portion of the second driver associated with a second subset of digit lines of the array of memory cells different from the first subset of digit lines.
6 . The apparatus of claim 5 , wherein:
the first portion of the first driver traverses a first edge of the subarray opposite a second edge of the subarray adjacent to the second subarray;
the second portion of the first driver traverses a first edge of the third subarray opposite a second edge of the third subarray adjacent to the fourth subarray;
the first portion of the second driver traverses a first edge of the second subarray opposite a second edge of the second subarray adjacent to the fourth subarray; and
the second portion of the second driver traverses a first edge of the fourth subarray opposite a second edge of the fourth subarray adjacent to the second subarray.
7 . The apparatus of claim 2 , wherein the first driver is associated with a subset of word lines of the array of memory cells and the second driver is associated with a subset of digit lines of the array of memory cells.
8 . The apparatus of claim 2 , wherein the first driver is a word line driver and the second driver is a sense amplifier multiplexed with digit lines.
9 . The apparatus of claim 1 , wherein the first substrate is coupled with a second interconnection layer between the first substrate and the first and second interconnects.
10 . The apparatus of claim 9 , wherein the first interconnection layer comprises a first metal of a first resistivity and the second interconnection layer comprises a second metal of a second resistivity higher than the first resistivity.
11 . The apparatus of claim 1 , wherein the first interconnect and the second interconnect traverse through areas positioned on a respective edge of the subarray excluding a word line driver or a digit liner driver.