System design for low temperature memory
A system can be designed with memory to operate in a low temperature environment. The low temperature memory can be customized for low temperature operation, having a gate stack to adjust a work function of the memory cell transistors to reduce the threshold voltage (Vth) relative to a standard memory device. The reduced temperature can improve the conductivity of other components within the memory, enabling increased memory array sizes, fewer vertical ground channels for stacked devices, and reduced operating power. Based on the differences in the memory, the memory controller can manage access to the memory device with adjusted control parameters based on lower leakage voltage for the memory cells and lower line resistance for the memory array.
1 . A system comprising:
a memory device with an array of memory cells, each memory cell having:
a transistor with an operating temperature in a range of approximately −25 C to +25 C having a gate stack with a combination of metal and highly doped polysilicon that adjusts a work function of the gate stack to reduce a threshold voltage (Vth) from a range of approximately 300-500 mV by 50-150 mV, to result in a reduced leakage voltage for the memory cell and a reduced line resistance for the array of memory cells as compared to the Vth of 300-500 mV; and
a capacitor; and
a memory controller coupled to the memory device, the memory controller to manage access to the memory device with adjusted control parameters based on the reduced leakage voltage for the memory cells and the reduced line resistance for the array at the operating temperature.
2 . The system of claim 1 , wherein the adjusted control parameters comprise a longer time between refreshes as compared to the Vth of 300-500 mV.
3 . The system of claim 1 , wherein the adjusted control parameters comprise a longer time between mitigation refreshes to address a row hammer condition as compared to the Vth of 300-500 mV.
4 . The system of claim 1 , wherein the adjusted control parameters comprise a lower operating voltage with a same signaling timing as compared to the Vth of 300-500 mV.
5 . The system of claim 1 , wherein the adjust control parameters comprises a higher communication frequency at a same operating voltage as compared to the Vth of 300-500 mV.
6 . The system of claim 1 , wherein the transistor includes a high-K dielectric between metal of the gate stack and a transistor channel, the high-K dielectric controlled for thickness to adjust the work function.
7 . The system of claim 1 , wherein the transistor includes an oxide between metal of the gate stack and a transistor channel, the oxide controlled for thickness to adjust the work function.
8 . The system of claim 1 , wherein a metal gate thickness of the transistor is controlled for thickness to adjust the work function.
9 . The system of claim 1 , wherein the gate stack has a metal gate composition controlled for composition to adjust the work function.
10 . The system of claim 1 , wherein the memory cells comprise single transistor, single capacitor dynamic random access memory (1T 1C DRAM) devices.
11 . The system of claim 1 , wherein the memory cells comprise an array of memory cells, with an array of wordlines and bitlines to control access to individual memory cells of the array, wherein the array has a capacity approximately 10-20% larger as compared to the Vth of 300-500 mV.
12 . The system of claim 1 , wherein the operating temperature comprises a subzero C temperature.
13 . The system of claim 1 , further comprising a control circuit to selectively drive voltage on a control line, wherein the control circuit is to provide a bias voltage having a same value as to the Vth of 300-500 mV.
14 . The system of claim 1 , further comprising a control circuit to selectively drive voltage on a control line, wherein the control circuit is to provide a bias voltage having a lower value as compared to the Vth of 300-500 mV.
15 . The system of claim 1 , wherein the memory device comprises a stacked memory device, with multiple memory dies coupled in a vertical stack.
16 . The system of claim 15 , wherein the multiple memory dies are coupled with through silicon vias (TSVs), wherein the stacked memory device has 10-20% fewer TSVs as compared to the Vth of 300-500 mV.
17 . A system comprising:
a memory device with an array of memory cells having:
a transistor with an operating temperature in a range of approximately −25 C to +25 C having a gate stack with a combination of metal and highly doped polysilicon that adjusts a work function of the gate stack to reduce a threshold voltage (Vth) from a range of approximately 300-500 mV by 50-150 mV, to result in a reduced leakage voltage for the memory cell and a reduced line resistance for the array of memory cells as compared to the Vth of 300-500 mV; and
a capacitor;
a processor device coupled to the memory device, the processor device including a memory controller coupled to the memory device, the memory controller to manage access to the memory device with adjusted control parameters based on the reduced leakage voltage for the memory cells and the reduced line resistance for the array at the operating temperature; and
a cooling system to cool the memory device to the range of approximately −25 C to +25 C.
18 . The system of claim 17 , further comprising:
a system on a chip (SOC) substrate, wherein the memory device is disposed on the SOC substrate and the processor device is disposed on the SOC substrate.
19 . The system of claim 17 , wherein the cooling system is to cool the processor device to the range of approximately −25 C to +25 C.
20 . The system of claim 17 , wherein the memory device comprises a stacked memory device, with multiple memory dies coupled in a vertical stack.