Semiconductor memory devices having enhanced sub-word line drivers therein
An embodiment provides a semiconductor memory device including a first word line extending along a first direction; a sub-word line driver including a first circuit and a second circuit that are connected to the first word line and are spaced apart from each other along the first direction, wherein the first circuit is configured to drive the first word line with a first voltage, and the second circuit is configured to drive the first word line with a second voltage that is different from the first voltage; and a memory cell connected to the first word line between the first circuit and the second circuit.
1 . A semiconductor memory device, comprising:
a first word line extending in a first direction;
a sub-word line driver including:
a first circuit and a second circuit that are connected to the first word line and are spaced apart from each other along the first direction; and
a third circuit disposed on an opposite side of the first circuit, with the first circuit between the second circuit and the third circuit, and the third circuit being connected to the first word line,
wherein the first circuit is configured to drive the first word line with a first voltage, the second circuit is configured to drive the first word line with a second voltage that is different from the first voltage, and the third circuit is configured to drive the first word line with the second voltage;
a first memory cell connected to the first word line and disposed between the first circuit and the second circuit along the first direction; and
a second memory cell connected to the first word line and disposed between the first circuit and the third circuit along the first direction.
2 . The semiconductor memory device of claim 1 , wherein the first circuit includes a first transistor connected between a first power supply and a first node to which the first word line is connected, and a second transistor that is connected to the first node and connected in series with the first transistor,
wherein the second circuit includes a third transistor connected between the first node and a second power supply,
wherein the first power supply is configured to supply the first voltage, and the second power supply is configured to supply the second voltage, and
wherein the first voltage is higher than the second voltage.
3 . The semiconductor memory device of claim 1 , wherein the first circuit is connected to the first word line at one end of a first portion of the first word line, and
the second circuit is connected to the first word line at the other end of the first portion of the first word line.
4 . The semiconductor memory device of claim 1 , wherein
the second circuit is connected to the first word line at one end of a first portion of the first word line, and
the third circuit is connected to the first word line at the other end of the first portion of the first word line.
5 . The semiconductor memory device of claim 1 , further comprising: a third memory cell connected to the first word line between the first circuit and the third circuit along the first direction.
6 . The semiconductor memory device of claim 1 , wherein
the second circuit and the third circuit have the same structure.
7 . The semiconductor memory device of claim 1 , further comprising:
a second word line that is adjacent to the first word line and extends in the first direction parallel to the first word line; and
a second sub-word line driver including a fourth circuit connected to the second word line, driving the second word line with the first voltage, and disposed adjacent to the second circuit of the first word line in a second direction, and a fifth circuit connected to the second word line, driving the second word line with the second voltage, and disposed adjacent to the first circuit of the first word line in the second direction.
8 . The semiconductor memory device of claim 1 , wherein the first circuit is configured to drive the first word line with the first voltage based on a first driving signal and a word line enable signal, and wherein the second circuit is configured to drive the first word line with the second voltage based on a second driving signal, the second driving signal being complementary to the first driving signal at least when the word line enable signal has a voltage that disables the first word line.
9 . A semiconductor memory device, comprising:
a first array of memory cells and a second array of memory cells;
a first word line electrically connected to a first memory cell within the first array of memory cells and a second memory cell within the second array of memory cells;
a first block extending adjacent a first side of the first array of memory cells, said first block including a first circuit connected to the first word line and configured to drive the first word line with a first voltage;
a second block extending adjacent a second side of the first array of memory cells that is opposite the first side, said second block including a second circuit connected to the first word line and configured to drive the first word line with a second voltage different from the first voltage; and
a third block including a third circuit connected to the first word line,
wherein the first word line extends through the first block, the second block, and the third block, and
wherein:
the second block is between the first block and the third block with the second array of memory cells as a single array of memory cells between the second block and the third block, and the third circuit is configured to drive the first word line with the first voltage, or
the first block is between the second block and the third block with the second array of memory cells as a single array of memory cells between the first block and the third block, and the third circuit is configured to drive the first word line with the second voltage.
10 . The semiconductor memory device of claim 9 , wherein the first circuit includes a pull-up transistor configured to pull-up the first word line to the first voltage, and the second circuit includes a pull-down transistor configured to pull-down the first word line to the second voltage.
11 . The semiconductor memory device of claim 10 , wherein:
the third block is disposed on an opposite side of the first block with respect to the second block with the first block between the second block and the third block, and
the third circuit is connected to the first word line and configured to drive the first word line with the second voltage.
12 . The semiconductor memory device of claim 11 , wherein the second circuit and the third circuit have the same structure.
13 . The semiconductor memory device of claim 12 , wherein
the second circuit and the third circuit are connected to the first word line at one end and the other end of the first word line, respectively.
14 . The semiconductor memory device of claim 10 , wherein:
the third block is disposed on an opposite side of the second block with respect to the first block with the second block between the first block and the third block, and
the third circuit is connected to the first word line and configured to drive the first word line with the first voltage.
15 . The semiconductor memory device of claim 14 , wherein the first circuit and the third circuit have the same structure.
16 . The semiconductor memory device of claim 15 , further comprising a fourth block disposed on an opposite side of the second block with respect to the third block,
wherein the first word line extends through the fourth block, and
wherein the fourth block includes a fourth circuit having a pull-down transistor connected to the first word line and configured to pull down the first word line to the second voltage.
17 . The semiconductor memory device of claim 10 , wherein the first circuit is connected to the first word line at one end of a first portion of the first word line, and the second circuit is connected to the first word line at the other end of the first portion of the first word line.
18 . A memory system, comprising:
a cell array including a plurality of memory cells connected to a plurality of word lines;
a memory controller configured to generate an address signal;
a row decoder configured to receive the address signal, output a first signal that selects a first word line from among the plurality of word lines based on the address signal, and output a plurality of driving signals; and
a first sub-word line driver including:
a first transistor connected to one end of the first word line, and configured to apply a first voltage to the first word line based on the first signal and a first driving signal among the plurality of driving signals,
a second transistor configured to apply a second voltage different from the first voltage to the first word line based on the first signal; and
a third transistor connected to the other end of the first word line and configured to apply the second voltage to the first word line based on a second driving signal complementary to the first driving signal.
19 . The memory system of claim 18 , further comprising:
a first sub-word line driver block disposed on a first side of the cell array and a second sub-word line driver block disposed on a second side of the cell array, the first side being opposite to the second side with respect to the cell array,
wherein the first word line extends across the first sub-word line driver block, the cell array, and the second sub-word line driver block; and
wherein the first transistor and the second transistor are disposed in the first sub-word line driver block, and the third transistor is disposed in the second sub-word line driver block.
20 . The memory system of claim 19 ,
wherein the row decoder is further configured to output a second signal selecting a second word line adjacent to the first word line among the plurality of word lines based on the address signal; and
wherein the memory system further includes a second sub-word line driver including:
a first transistor that is connected to one end of the second word line, configured to apply the first voltage to the second word line based on the second signal and a third driving signal among the plurality of driving signals, and disposed in the second sub-word line driver block;
a second transistor that is configured to apply the second voltage to the second word line based on the second signal, and is disposed in the second sub-word line driver block; and
a third transistor that is connected to another end of the second word line, configured to apply the second voltage to the second word line based on a fourth driving signal complementary to the third driving signal, and disposed in the first sub-word line driver block.