Memory device architecture using multiple physical cells per bit to improve read margin and to alleviate the need for managing demarcation read voltages
The application relates to an architecture that allows for less precision of demarcation read voltages by combining two physical memory cells into a single logical bit. Reciprocal binary values may be written into the two memory cells that make up a memory pair. When activated using bias circuitry and address decoders the memory cell pair creates current paths having currents that may be compared to detect a differential signal. The application is also directed to writing and reading memory cell pairs.
1 . A device, comprising:
a plurality of memory cells arranged in a plurality of memory cell pairs each connected to a word line and a bit line; and
a controller configured to perform a write operation comprising:
select a first memory cell of a memory cell pair of the plurality of memory cell pairs;
write a single bit value to the first memory cell;
select a second memory cell of the memory cell pair, wherein the first memory cell and the second memory cell are not adjacent on each of their respective word lines and bit lines; and
write an inverse of the single bit value to the second memory cell,
wherein the first memory cell is individually selected at a first time using an address decoder.
2 . The device of claim 1 , wherein the controller is further configured to deselect, using the address decoder, the first memory cell after the single bit value is written to the first memory cell.
3 . The device of claim 2 , wherein deselection of the first memory cell further occurs prior to selection of the second memory cell using the address decoder.
4 . The device of claim 1 , wherein the second memory cell is individually selected at a second time using the address decoder, wherein the first time is different from the second time.
5 . The device of claim 1 , wherein the plurality of memory cells comprises a plurality of different decks of memory cells.
6 . The device of claim 5 , wherein the first memory cell is located on a first deck of the different decks of memory cells and the second memory cell is located on a second deck of the different decks of memory cells.
7 . The device of claim 6 , wherein the first deck is stacked on top of the second deck.
8 . The device of claim 6 , wherein the second deck is stacked on top of the first deck.
9 . The device of claim 6 , wherein a third deck of the different decks of memory cells is located between the first deck and the second deck.
10 . The device of claim 6 , wherein the first memory cell and the second memory cell are located on a same row shared between the first deck and the second deck.
11 . A device, comprising:
a plurality of memory cells each connected to a word line and a bit line, each of the plurality of memory cells further arranged in different layers that are stacked on one another; and
a controller configured to perform a write operation comprising:
select a first memory cell of a memory cell pair;
write a single bit value to the first memory cell;
select a second memory cell of the memory cell pair, wherein the first memory cell is on a first layer of the different layers and the second memory cell is on a second layer of the different layers, and wherein the first memory cell and the second memory cell are not adjacent on each of their respective word lines and bit lines; and
write an inverse of the single bit value to the second memory cell,
wherein the first memory cell is individually selected at a first time using an address decoder.
12 . The device of claim 11 , wherein the first layer is stacked on top of the second layer.
13 . The device of claim 11 , wherein the second layer is stacked on top of the first layer.
14 . The device of claim 11 , wherein a third layer of the different layers is located between the first layer and the second layer.
15 . The device of claim 11 , wherein the first memory cell and the second memory cell are located on a same row shared between the first layer and the second layer.
16 . A device, comprising:
a plurality of memory cells each connected to a word line and a bit line, each of the plurality of memory cells further arranged in a plurality of different decks of memory cells; and
a controller configured to perform a read operation comprising:
select a first memory cell of a memory cell pair and a second memory cell of the memory cell pair; and
determine a binary value stored in the memory cell pair based on a comparison of respective currents through each of the first memory cell and the second memory cell of the memory cell pair,
wherein the first memory cell is located on a first deck of the different decks and the second memory cell is located on a second deck of the different decks, and
wherein the first memory cell and the second memory cell are not adjacent on each of their respective word lines and bit lines,
wherein the first memory cell is individually selected at a first time using an address decoder.
17 . The device of claim 16 , wherein the first deck is stacked on top of the second deck or the second deck is stacked on top of the first deck.
18 . The device of claim 16 , wherein a third deck of the different decks of memory cells is located between the first deck and the second deck.
19 . The device of claim 16 , wherein the first memory cell and the second memory cell are located on a same row shared between the first deck and the second deck.