Memory and method related to tracking memory

1 . A memory, comprising:

a memory cell array;

a tracking cell column, coupled to the memory cell array and comprising:

a first tracking cell, configured to track an operation of a first row of memory cells of the memory cell array; and

a second tracking cell, configured to track an operation of a second row of memory cells of the memory cell array;

a first tracking word line, coupled to the first tracking cell; and

a second tracking word line, coupled to the second tracking cell,

wherein one of the first tracking word line and the second tracking word line is selected in response to a control signal from a counter circuit.

2 . The memory according to claim 1 , wherein

a tracking word line signal is transmitted on one of the first tracking word line and the second tracking word line during a first cycle of a clock signal, and

the tracking word line signal is transmitted on another one of the first tracking word line and the second tracking word line during a second cycle of the clock signal.

3 . The memory according to claim 1 , further comprising:

a master tracking word line, configured to transmit a tracking word line signal; and

a controller, comprising:

a demultiplexer, coupled to the master tracking word line, the first tracking word line, and the second tracking word line, and configured to perform the selection of the first tracking word line and the second tracking word line to transmit the tracking word line signal from the master tracking word line.

4 . The memory according to claim 3 , wherein the controller further comprises:

a clock generator, coupled to the demultiplexer, and configured to receive a clock signal and generate an inter clock signal based on the clock signal, wherein the inter clock signal is used to generate the tracking word line signal.

5 . The memory according to claim 3 , wherein the demultiplexer is further configured to:

select one of the first tracking word line and the second tracking word line to transmit the tracking word line signal during a first cycle of the clock signal, and

select another one of the first tracking word line and the second tracking word line to transmit the tracking word line signal during a second cycle of the clock signal.

6 . The memory according to claim 3 , wherein the controller further comprises:

the counter circuit, coupled to the multiplexer, and configured to generate the control signal, wherein the control signal is configured as one of a first value and a second value, and the demultiplexer is further configured to:

select one of the first tracking word line and the second tracking word line to transmit the tracking word line signal in response to receiving the control signal configured as the first value; and

select another one of the first tracking word line and the second tracking word line to transmit the tracking word line signal in response to receiving the control signal configured as the second value.

7 . The memory according to claim 1 , wherein the tracking cell column further comprises:

a third tracking cell to an n-th tracking cell, respectively configured to track an operation of one row of memory cells of the memory cell array, wherein n is an integer larger than two, and the memory further comprises:

a third tracking word line to an n-th tracking word line, respectively coupled to one of the third tracking cell to the n-th tracking cell.

8 . The memory according to claim 7 , further comprising:

a master tracking word line, configured to transmit a tracking word line signal; and

a controller, comprising:

a demultiplexer, coupled to the master tracking word line and the first tracking word line to the n-th tracking word line, and configured to select one of the first tracking word line to the n-th tracking word line to transmit the tracking word line signal from the master tracking word line according to a control signal, wherein the control signal is configured as one of n values, and the n values are encoded in log 2 n bits.

9 . The memory according to claim 1 , further comprising:

a first tracking bit line, coupled to the first tracking cell; and

a second tracking bit line, coupled to the second tracking cell.

10 . The memory according to claim 9 , wherein

a tracking bit line signal is transmitted on one of the first tracking bit line and the second tracking bit line during a first cycle of a clock signal, and

the tracking bit line signal is transmitted on another one of the first tracking bit line and the second tracking bit line during a second cycle of the clock signal.

11 . A method related to tracking a memory, comprising:

providing a tracking cell column, a first tracking word line, and a second tracking word line, wherein the tracking cell column comprises a first tracking cell coupled to the first tracking word line and a second tracking cell coupled to the second tracking word line;

tracking, through the first tracking cell, an operation of a first row of memory cells with a tracking word line signal transmitted on the first tracking word line; and

tracking, through the second tracking cell, an operation of a second row of memory cells with the tracking word line signal transmitted on the second tracking word line,

wherein one of the first tracking word line and the second tracking word line is selected in response to a control signal from a counter circuit.

12 . The method according to claim 11 , wherein

tracking, through the first tracking cell, the operation of the first row of memory cells comprises:

transmitting the tracking word line signal on one of the first tracking word line and the second tracking word line during a first cycle of a clock signal, and

tracking, through the second tracking cell, the operation of the second row of memory cells comprises:

transmitting the tracking word line signal on another one of the first tracking word line and the second tracking word line during a second cycle of the clock signal.

13 . The method according to claim 11 , further comprising:

selecting one of the first tracking word line and the second tracking word line to transmit the tracking word line signal.

14 . The method according to claim 13 , further comprising:

receive a clock signal;

generate an inter clock signal based on the clock signal; and

generate the tracking word line signal based on the inter clock signal.

15 . The method according to claim 13 , further comprising:

select one of the first tracking word line and the second tracking word line to transmit the tracking word line signal during a first cycle of the clock signal, and

select another one of the first tracking word line and the second tracking word line to transmit the tracking word line signal during a second cycle of the clock signal.

16 . The method according to claim 13 , further comprising:

generating the control signal by the counter circuit, wherein the control signal is configured as one of a first value and a second value;

selecting one of the first tracking word line and the second tracking word line to transmit the tracking word line signal in response to the control signal being configured as the first value; and

selecting another one of the first tracking word line and the second tracking word line to transmit the tracking word line signal in response to the control signal being configured as the second value.

17 . The method according to claim 11 , further comprising:

providing a third tracking cell to an n-th tracking cell and a third tracking word line to an n-th tracking word line, wherein the third tracking word line to the n-th tracking word line respectively coupled to one of the third tracking cell to the n-th tracking cell; and

tracking, through one of the third tracking cell to the n-th tracking cell, an operation of one row of memory cells.

18 . The method according to claim 11 , further comprising:

providing a first tracking bit line coupled to the first tracking cell and a second tracking bit line coupled to the second tracking cell;

transmitting a tracking bit line signal on one of the first tracking bit line and the second tracking bit line during a first cycle of a clock signal, and

transmitting the tracking bit line signal on another one of the first tracking bit line and the second tracking bit line during a second cycle of the clock signal.

19 . A memory, comprising:

a memory cell array;

a tracking cell column, coupled to the memory cell array and comprising:

a first tracking cell, configured to track an operation of a first row of memory cells of the memory cell array; and

a second tracking cell, configured to track an operation of a second row of memory cells of the memory cell array;

a first tracking bit line, coupled to the first tracking cell; and

a second tracking bit line, coupled to the second tracking cell

wherein one of the first tracking bit line and the second tracking bit line is selected in response to a control signal from a counter circuit.

20 . The memory according to claim 19 , wherein

a tracking bit line signal is transmitted to a master tracking bit line from one of the first tracking bit line and the second tracking bit line during a first cycle of a clock signal, and

the tracking bit line signal is transmitted to a master tracking bit line from another one of the first tracking bit line and the second tracking bit line during a second cycle of the clock signal.