Fly shared bit line on 4-CPP static random access memory (SRAM) cell and array

Inventors: Yi-Hsin Nien (Hsinchu, TW); Chih-Yu Lin (Hsinchu, TW); Hidehiro Fujiwara (Hsinchu, TW); Yen-Huei Chen (Hsinchu, TW)

Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.

G11C11/419 H10B10/12 H10B10/18

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Quick Facts

Patent No.: US 12700454
App. No.: 18/328,095
Granted: Aug 4, 2026
Kind: B2

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Abstract

A semiconductor device includes a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell operatively arranged along a first one of a plurality of columns, and operatively arranged in a first one, a second one, a third one, and a fourth one of a plurality of rows, respectively. The first column operatively corresponds to a first pair of bit lines and a second pair of bit lines. The first to fourth rows operatively correspond to a first word line, a second word line, a third word line, and a fourth word line, respectively. The first pair of bit lines are operatively coupled to the first and second memory cells. The second pair of bit lines are operatively coupled to the third and fourth memory cells.

Claims (40)

1 . A semiconductor device, comprising:

a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell operatively arranged along a first one of a plurality of columns, and operatively arranged in a first one, a second one, a third one, and a fourth one of a plurality of rows, respectively;

wherein the first column operatively corresponds to a first pair of bit lines and a second pair of bit lines, and the first to fourth rows operatively correspond to a first word line, a second word line, a third word line, and a fourth word line, respectively;

wherein the first pair of bit lines are operatively coupled to the first and second memory cells, and the second pair of bit lines are operatively coupled to the third and fourth memory cells;

wherein the first pair of bit lines, along a first lateral direction, physically extend across a first portion of a substrate where the first and second memory cells are formed and terminates at a second portion of the substrate where the third and fourth memory cells are formed, while the second pair of bit lines, also along the first lateral direction, physically extend across both of the first portion and the second portion;

wherein the first pair of bit lines are formed in a first one of a plurality of metallization layers disposed over the substrate, while the second pair of bit lines each have a first portion formed in the first metallization layer and a second portion formed in a second one of the plurality of metallization layers, and

wherein the first memory cell is physically arranged next to the second memory cell along a second lateral direction, and the third memory cell is physically arranged next to the fourth memory cell along the second lateral direction, the second lateral direction being perpendicular to the first lateral direction.

2 . The semiconductor device of claim 1 , wherein the first to fourth memory cells are each formed based on a four contacted polysilicon pitch (4CPP) transistor architecture.

3 . The semiconductor device of claim 1 , wherein the first memory cell is aligned with but physically spaced from the third memory cell along the first lateral direction, and the second memory cell is aligned with but physically spaced from the fourth memory cell along the first lateral direction.

4 . The semiconductor device of claim 3 , wherein the first and second memory cells belong to a first memory bank, and the third and fourth memory cells belong to a second memory bank.

5 . The semiconductor device of claim 1 , wherein at least one portion of each of the first pair of bit lines and the second pair of bit lines are formed in a same one of a plurality of metallization layers disposed over the substrate.

6 . The semiconductor device of claim 1 , wherein the first portion of each of the second pair of bit lines extends in the first lateral direction, and the second portion of each of the second pair of bit lines extends in the second lateral direction.

7 . The semiconductor device of claim 1 , wherein the second pair of bit lines further comprises a third portion formed in a third one of the plurality of metallization layers.

8 . The semiconductor device of claim 7 , wherein the first portion and third portion of each of the second pair of bit lines extend in the first lateral direction, and the second portion of each of the second pair of bit lines extends in the second lateral direction.

9 . A semiconductor device, comprising:

a first memory array including a plurality of first memory cells that are formed over a first portion of a substrate, wherein the plurality of first memory cells comprises a first memory cell and a second memory cell;

a second memory array including a plurality of second memory cells that are formed over a second portion of the substrate, wherein the second portion is physically separated from the first portion along a first lateral direction, wherein the plurality of second memory cells comprises a third memory cell and a fourth memory cell;

a first pair of bit lines physically extend across the first portion and terminates at the second portion; and

a second pair of bit lines physically extend across both of the first portion and the second portion;

10 . The semiconductor device of claim 9 , wherein the first pair of bit lines are operatively coupled only to the first memory cells, and the second pair of bit lines are operatively coupled only to the second memory cells.

11 . The semiconductor device of claim 9 , wherein the first memory cells are physically arranged side-by-side along a second lateral direction perpendicular to the first lateral direction, and the second memory cells are physically arranged side-by-side along the second lateral direction.

12 . The semiconductor device of claim 11 , wherein adjacent one of the first memory cells are operatively coupled to respectively different word lines, and adjacent one of the second memory cells are operatively coupled to respectively different word lines.

13 . The semiconductor device of claim 9 , wherein at least one portion of each of the first pair of bit lines and the second pair of bit lines are formed in a same one of a plurality of metallization layers disposed over the substrate.

14 . The semiconductor device of claim 9 , wherein the second pair of bit lines further comprises a third portion formed in a third one of the plurality of metallization layers.

15 . The semiconductor device of claim 9 , wherein the first and second memory cells are each formed based on a four contacted polysilicon pitch (4CPP) transistor architecture.

16 . A method for making memory arrays, comprising:

arranging first and second memory cells over a first portion of a substrate and third and fourth memory cells over a second portion of the substrate, the first portion being separated from the second portion along a first lateral direction, wherein each of the first to four memory cells comprises a plurality of transistors formed based on a four contacted polysilicon pitch (4CPP) architecture;

connecting a first word line and a second word line to the first memory cell and the second memory cell, respectively;

connecting a third word line and a fourth word line to the third memory cell and the fourth memory cell, respectively;

connecting a first pair of bit lines to the first and second memory cells; and

connecting a second pair of bit lines to the third and fourth memory cells;

wherein the first pair of bit lines, along the first lateral direction, physically extend across the first portion and terminates at the second portion, and the second pair of bit lines, along the first lateral direction, physically extend across both of the first portion and the second portion;

wherein the first and second memory cells are physically arranged next to each other along a second lateral direction perpendicular to the first lateral direction, and the third and fourth memory cells are physically arranged next to each other along the second lateral direction.

17 . The method of claim 16 , wherein the first and second memory cells belong to a first memory bank, and the third and fourth memory cells belong to a second memory bank.

18 . The method of claim 16 , wherein the second pair of bit lines further comprises a third portion formed in a third one of the plurality of metallization layers.

19 . The method of claim 18 , wherein the first portion and third portion of each of the second pair of bit lines extend in the first lateral direction, and the second portion of each of the second pair of bit lines extends in the second lateral direction.

20 . The method of claim 16 , wherein the first memory cell is aligned with but physically spaced from the third memory cell along the first lateral direction, and the second memory cell is aligned with but physically spaced from the fourth memory cell along the first lateral direction.