3D cell and array structures
Various 3D cells, array structures, and processes are disclosed. In an embodiment, a 3D cell structure includes a NOR-type memory cell array having rows of memory cells, and each memory cell stores data that controls a cell current for that memory cell. The structure also includes bit lines connected to the rows of memory cells, and each bit line is connected to one memory cell in each of row. The cell structure also includes source lines connected to the rows of memory cells, respectively, and each source line is connected to all the memory cells of a corresponding row of memory cells. The structure is configured so that input signals applied to the bit lines cause cell currents to flow through the memory cells, and in each row of memory cells, selected cell currents combine to form a row cell current that flows on the associated source line.
1 . A 3D memory array architecture, comprising:
a plurality of memory units arranged as a stack, each memory unit comprising a memory cell array including one or more rows of memory cells, and wherein each memory cell is configured to store data that controls a cell current for that memory cell;
row source lines connected to the rows of memory cells, respectively, wherein each row source line is connected to memory cells of a corresponding row, and wherein the row source lines are coupled to a common source line for each memory unit;
a word line and select-gate decoder configured to activate selected memory cells in the memory cell arrays using word lines and select-gate lines;
bit lines connected to the memory cell arrays, wherein, in each memory cell array, each bit line is connected to one memory cell in each of the one or more rows of memory cells within that memory cell array;
a bit line decoder connected between external bit line circuits and the bit lines of the memory units, wherein the bit line decoder is configured to selectively couple bit line signals between the external bit line circuits and a selected set of the bit lines, and wherein the selective coupling is performed such that a total number of external bit line circuits can be less than a total number of bit lines;
a source line decoder connected between the common source lines of the memory units and external source line circuits, wherein the source line decoder is configured to selectively couple common source line signals between a selected set of the common source lines and the external source line circuits, and wherein the selective coupling is performed such that a total number of external source line circuits can be less than a total number of common source lines;
wherein the 3D memory array architecture has a configurable direction such that, in a first direction, signals flow from the external bit line circuits through the bit line decoder, the memory cell arrays, and the source line decoder to the external source line circuits, and in a second direction, signals flow from the external source line circuits through the source line decoder, the memory cell arrays, and the bit line decoder to the external bit line circuits; and
wherein, during operation, the word line and select-gate decoder, the bit line decoder, and the source line decoder have multiple-select functions that select any number of memory units, bit lines, and source lines in any locations according to a selected task.
2 . The 3D memory array architecture of claim 1 , wherein the memory cells comprise one of floating body cells, flash memory cells, resistive random-access memory cells, ferroelectric random-access memory cells, magneto-resistive random-access memory cells, phase-change memory cells, and mem-transistor cells.
3 . The 3D memory array architecture of claim 1 , wherein the bit lines are grouped into bit line pairs and each input signal is converted into complementary input signals that are supplied to a corresponding bit line pair.
4 . The 3D memory array architecture of claim 1 , wherein the external bit line circuits function as input circuits in the first direction and function as output circuits in the second direction, and wherein the external source line circuits function as output circuits in the first direction and function as input circuits in the second direction.
5 . The 3D memory array architecture of claim 1 , wherein the 3D memory array architecture implements a neural network and wherein the memory cells are configured to implement synapses in the neural network.
6 . The 3D memory array architecture of claim 5 , wherein for each memory cell representing a synapse, an associated threshold voltage represents a synapse weight.
7 . The 3D memory array architecture of claim 1 , wherein the 3D memory array architecture is configured to perform in-memory computing functions by combining cell currents from selected memory cells to perform a summation function.
8 . The 3D memory array architecture of claim 1 , wherein the word line and select-gate decoder, the bit line decoder, and the source line decoder have multiple-select functions that select any number of memory units, bit lines, and source lines in any locations according to a desired task.
9 . The 3D memory array architecture of claim 1 , wherein, during operation, the word line and select-gate decoder selects multiple memory units and, for each selected memory unit, selects a word line and a select-gate line.
10 . The 3D memory array architecture of claim 1 , wherein each memory unit comprises a plurality of row source lines coupled to the common source line for the memory unit.
11 . The 3D memory array architecture of claim 1 , wherein, in the first direction, the bit line decoder selectively couples input signals from the external circuits to a selected set of the bit lines and the source line decoder selectively couples output signals from the selected set of the common source lines to the external source line circuits.
12 . The 3D memory array architecture of claim 1 , wherein the first direction corresponds to forward-propagation of the neural network and the second direction corresponds to back-propagation for training the neural network.
13 . The 3D memory array architecture of claim 1 , wherein the source line decoder is configured to selectively couple the selected set of the common source lines to the external source line circuits such that a total number of external source line circuits is less than a total number of common source lines.
14 . The 3D memory array architecture of claim 1 , wherein the bit line decoder is configured to selectively couple the selected set of the bit lines to the external bit line circuits such that a total number of external bit line circuits is less than a total number of bit lines.
15 . A 3D memory array architecture, comprising:
a plurality of memory units arranged as a stack, each memory unit comprising a memory cell array including one or more rows of memory cells, and wherein each memory cell is configured to store data that controls a cell current for that memory cell;
row source lines connected to the rows of memory cells, respectively, wherein each row source line is connected to memory cells of a corresponding row, and wherein the row source lines are coupled to a common source line for each memory unit;
word lines connected to the rows of memory cells, respectively, wherein each word line is connected to all memory cells of a corresponding row of memory cells;
bit lines connected to the memory units, wherein, in each memory cell array, each bit line is connected to one memory cell in each of the one or more rows of memory cells within that memory cell array;
a word line and select-gate decoder configured to activate selected memory cells using the word lines and select-gate lines;
a bit line decoder connected between external bit line circuits and the bit lines of the memory units, wherein the bit line decoder is configured to selectively couple bit line signals between the external bit line circuits and a selected set of the bit lines, and wherein the selective coupling is performed such that a total number of external bit line circuits can be less than a total number of bit lines; and
wherein, during operation, input signals applied to the word lines cause cell currents to flow through selected memory cells, and wherein, for a selected bit line, selected cell currents combine to form a bit line cell current that flows on the selected bit line and is coupled by the bit line decoder to the external bit line circuits;
wherein, during operation, the word line and select-gate decoder and the bit line decoder are configured to perform multiple-select operations that select any number of memory units, word lines, and bit lines in any locations according to a desired task.
16 . The 3D memory array architecture of claim 15 , wherein the memory cells comprise one of floating body cells, flash memory cells, resistive random-access memory cells, ferroelectric random-access memory cells, magneto-resistive random-access memory cells, phase-change memory cells, and mem-transistor cells.
17 . The 3D memory array architecture of claim 15 , wherein the word lines are grouped into word line pairs and each input signal is converted into complementary input signals (WL 0 + and WL 0 −) that are supplied to a corresponding word line pair.
18 . The 3D memory array architecture of claim 15 , wherein the bit lines are connected to output circuits of the 3D cell structure and the word lines are connected to input circuits of the 3D cell structure.
19 . The 3D memory array architecture of claim 15 , wherein the 3D cell structure forms a neural network and wherein the memory cells are configured to act as synapses in the neural network, and wherein for each memory cell representing a synapse, an associated threshold voltage represents a synapse weight.
20 . The 3D memory array architecture of claim 15 , wherein the 3D memory array architecture is configured to perform in-memory computing functions by combining cell currents from selected memory cells to perform a summation function.