Controlling pillar voltage using wordline boost voltage and select gate leakage during all levels programming of a memory device
Control logic in a memory device initiates a program operation including a first phase including applying a ramping voltage level to a set of wordlines of a memory device to boost a set of pillar voltages and a second phase including applying a set of programming pulses to a wordline associated with one or more memory cells of the memory device to be programmed to a set of programming levels, wherein each programming level of the set of programming levels is programmed by each programming pulse. During the first phase of the program operation, a first voltage applied to a drain-side select line (SGD) is adjusted from a first SGD voltage level to a second SGD voltage level.
1 . A memory device comprising:
a memory array comprising a plurality of memory cells; and
control logic, operatively coupled with the memory array, to perform operations comprising:
initiating a program operation comprising a first phase comprising applying a ramping voltage level to a set of wordlines of the memory device to boost a set of pillar voltages and a second phase comprising applying a set of programming pulses to a wordline associated with one or more memory cells of the memory array to be programmed to a set of programming levels, wherein each programming level of the set of programming levels is programmed by each programming pulse of the set of programming pulses; and
during the first phase of the program operation, adjusting a first voltage applied to a drain-side select line (SGD) from a first SGD voltage level to a second SGD voltage level.
2 . The memory device of claim 1 , wherein the first SGD voltage level is greater than the second SGD voltage level.
3 . The memory device of claim 1 , wherein adjusting the first voltage applied to the SGD causes SGD leakage.
4 . The memory device of claim 1 , the operations further comprising, during the first phase of program operation, adjusting a second voltage applied to a source-side select line (SGS) from a first SGS voltage level to a second SGS voltage level.
5 . The memory device of claim 4 , wherein the first SGS voltage level is greater than the second SGS voltage level.
6 . The memory device of claim 1 , the operations further comprising incrementing the ramping voltage level by a step voltage amount for a subset of the set of pillars.
7 . The memory device of claim 6 , wherein the ramping voltage level is not increased during boosting of a sixth pillar associated with a sixth programming level of the set of programming levels and a seventh pillar associated with a seventh programming level of the set of programming levels.
8 . A method comprising:
initiating a program operation comprising a first phase comprising applying a ramping voltage level to a set of wordlines of a memory device to boost a set of pillar voltages and a second phase comprising applying a set of programming pulses to a wordline associated with one or more memory cells of the memory device to be programmed to a set of programming levels, wherein each programming level of the set of programming levels is programmed by each programming pulse of the set of programming pulses; and
during the first phase of the program operation, adjusting a first voltage applied to a drain-side select line (SGD) from a first SGD voltage level to a second SGD voltage level.
9 . The method of claim 8 , wherein the first SGD voltage level is greater than the second SGD voltage level.
10 . The method of claim 8 , wherein adjusting the first voltage applied to the SGD causes SGD leakage.
11 . The method of claim 8 , further comprising, during the first phase of program operation, adjusting a second voltage applied to a source-side select line (SGS) from a first SGS voltage level to a second SGS voltage level.
12 . The method of claim 11 , wherein the first SGS voltage level is greater than the second SGS voltage level.
13 . The method of claim 8 , further comprising incrementing the ramping voltage level by a step voltage amount for a subset of the set of pillars.
14 . The method of claim 13 , wherein the ramping voltage level is not increased during boosting of a sixth pillar associated with a sixth programming level of the set of programming levels and a seventh pillar associated with a seventh programming level of the set of programming levels.
15 . A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
initiating a program operation comprising a first phase comprising applying a ramping voltage level to a set of wordlines of a memory device to boost a set of pillar voltages and a second phase comprising applying a set of programming pulses to a wordline associated with one or more memory cells of a memory device to be programmed to a set of programming levels, wherein each programming level of the set of programming levels is programmed by each programming pulse of the set of programming pulses; and
during the first phase of the program operation, adjusting a first voltage applied to a drain-side select line (SGD) from a first SGD voltage level to a second SGD voltage level.
16 . The non-transitory computer-readable storage medium of claim 15 , wherein the first SGD voltage level is greater than the second SGD voltage level.
17 . The non-transitory computer-readable storage medium of claim 15 , wherein adjusting the first voltage applied to the SGD causes SGD leakage.
18 . The non-transitory computer-readable storage medium of claim 15 , the operations further comprising, during the first phase of program operation, adjusting a second voltage applied to a source-side select line (SGS) from a first SGS voltage level to a second SGS voltage level.
19 . The non-transitory computer-readable storage medium of claim 18 , wherein the first SGS voltage level is greater than the second SGS voltage level.
20 . The non-transitory computer-readable storage medium of claim 15 , further comprising incrementing the ramping voltage level by a step voltage amount for a subset of the set of pillars, wherein the ramping voltage level is not increased during boosting of a sixth pillar associated with a sixth programming level of the set of programming levels and a seventh pillar associated with a seventh programming level of the set of programming levels.