Memory device and method of operating memory device for programming select transistors
An operating method of a memory device may include performing a pre-program operation on selection transistors that are included in strings, wherein each of the strings comprises a first source selection transistor, a second source selection transistor, a plurality of memory cells, and a drain selection transistor that are sequentially coupled, and performing an erase operation and a fine program operation on at least one of the selection transistors.
1 . An operating method of a memory device, comprising:
prior to performing an erase operation, performing a pre-program operation on selection transistors that are included in strings, wherein each of the strings comprises a first source selection transistor, a second source selection transistor, a plurality of memory cells, and a drain selection transistor that are sequentially coupled; and
performing the erase operation and a fine program operation on at least one of the selection transistors,
wherein the performing of the pre-program operation comprises:
performing an entire program operation including applying a program voltage to all source selection transistors included in the strings; and
performing an additional program operation including repeatedly applying the program voltage to second source selection transistors included in the strings until a pass count for target second source selection transistors for the additional program operation is greater than a reference pass count, wherein no additional program operation is performed on first source selection transistors included in the strings in the pre-program operation; and
wherein the performing of the fine program operation comprises repeatedly applying the program voltage to target second source selection transistors for the fine program operation until a fail count for the target second source selection transistors for the fine program operation is less than a first reference fail count.
2 . The operating method according to claim 1 , wherein
the program voltage is applied a predetermined number of times while being increased in the entire program operation.
3 . The operating method according to claim 1 , wherein the performing of the additional program operation comprises:
a first process of applying the program voltage to the second source selection transistors;
a second process of verifying threshold voltages of the target second source selection transistors for the additional program operation by using a verification voltage; and
a third process of repeating the first process and the second process while increasing the program voltage incrementally until the pass count for the target second source selection transistors for the additional program operation is greater than the reference pass count.
4 . The operating method according to claim 3 , wherein the performing of the additional program operation further comprises:
a fourth process of determining new target second source selection transistors for the additional program operation when the pass count is greater than the reference pass count;
a fifth process of verifying threshold voltages of the new target second source selection transistors by using the verification voltage; and
a sixth process of repeatedly performing the first process and the second process on the new target second source selection transistors while increasing the program voltage incrementally until a pass count for the new target second source selection transistors is greater than the reference pass count.
5 . The operating method according to claim 1 , wherein the performing of the pre-program operation comprises:
a first process of applying the program voltage to target drain selection transistors for the pre-program operation among drain selection transistors that are included in the strings;
a second process of verifying threshold voltages of the target drain selection transistors by using a verification voltage; and
a third process of repeating the first process and the second process while increasing the program voltage incrementally until a fail count for the target drain selection transistors is less than a second reference fail count.
6 . The operating method according to claim 5 , wherein the performing of the pre-program operation further comprises:
a fourth process of determining new target drain selection transistors for the pre-program operation when the fail count is less than the second reference fail count; and
a fifth process of repeatedly performing the first process and the second process on the new target drain selection transistors while increasing the program voltage incrementally until a fail count for the new target drain selection transistors is less than the second reference fail count.
7 . The operating method according to claim 1 , wherein the performing of the erase operation and the fine program operation comprises:
a first process of performing the erase operation on target drain selection transistors for the fine program operation among drain selection transistors that are included in the strings;
a second process of applying the program voltage to the target drain selection transistors;
a third process of verifying threshold voltages of the target drain selection transistors by using a verification voltage;
a fourth process of controlling a program for pass transistors, among the target drain selection transistors, so that the program is prohibited; and
a fifth process of repeating the second process, the third process, and the fourth process while increasing the program voltage incrementally until a fail count for the target drain selection transistors is less than a third reference fail count.
8 . The operating method according to claim 7 , wherein the performing of the erase operation and the fine program operation further comprises:
a sixth process of determining new target drain selection transistors for the fine program operation when the fail count is less than the third reference fail count;
a seventh process of performing the erase operation on the new target drain selection transistors; and
an eighth process of repeatedly performing the second process, the third process, and the fourth process on the new target drain selection transistors while increasing the program voltage incrementally until a fail count for the new target drain selection transistors is less than the third reference fail count.
9 . The operating method according to claim 1 , wherein the performing of the erase operation and the fine program operation comprises:
a first process of performing the erase operation on the target second source selection transistors for the fine program operation;
a second process of applying the program voltage to the target second source selection transistors for the fine program operation;
a third process of verifying threshold voltages of the target second source selection transistors for the fine program operation by using a second verification voltage;
a fourth process of controlling a program for pass transistors, among the target second source selection transistors for the fine program operation, so that the program is prohibited; and
a fifth process of repeating the second process, the third process, and the fourth process while increasing the program voltage incrementally until the fail count for the target second source selection transistors for the fine program operation is less than the first reference fail count.
10 . The operating method according to claim 9 , wherein the performing of the erase operation and the fine program operation further comprises:
a sixth process of determining new target second source selection transistors for the fine program operation when the fail count is less than the first reference fail count;
a seventh process of performing the erase operation on the new target second source selection transistors; and
an eighth process of repeatedly performing the second process, the third process, and the fourth process on the new target second source selection transistors while increasing the program voltage incrementally until a fail count for the new target second source selection transistors is less than the first reference fail count.
11 . A method of operating a memory device, comprising:
performing a first pre-program operation on selection transistors that are included in strings, wherein each of the strings comprises a plurality of memory cells that are coupled between the selection transistors; and
sequentially performing an erase operation, a second pre-program operation, a slow transistor masking operation, and a fine program operation on target selection transistors, among the selection transistors that are included in the strings.
12 . The method according to claim 11 , wherein the performing of the second pre-program operation comprises applying a program voltage to the target selection transistors a predetermined number of times while increasing the program voltage incrementally.
13 . The method according to claim 12 , wherein the performing of the slow transistor masking operation comprises:
verifying threshold voltages of the target selection transistors by using a first verification voltage; and
masking slow transistors, among the target selection transistors, by treating each of the slow transistors as a pass transistor.
14 . The method according to claim 13 , wherein the performing of the fine program operation comprises:
a first process of applying the program voltage to the target selection transistors;
a second process of verifying threshold voltages of the target selection transistors by using a second verification voltage;
a third process of controlling a program for pass transistors, among the target selection transistors, so that the program is prohibited; and
a fourth process of repeating the first process, the second process, and the third process while increasing the program voltage incrementally until a fail count for the target selection transistors is less than a reference fail count.
15 . The method according to claim 14 , wherein the pass transistors comprise a selection transistor having a threshold voltage that is lower than the first verification voltage, among the target selection transistors, and a selection transistor having a threshold voltage that is higher than the second verification voltage, among the target selection transistors.
16 . The method according to claim 14 , further comprising:
determining new target selection transistors when the fail count is less than the reference fail count; and
sequentially performing the erase operation, the second pre-program operation, the slow transistor masking operation, and the fine program operation on the new target selection transistors.
17 . A memory device comprising:
a memory block comprising a plurality of strings, each of the strings comprising selection transistors and a plurality of memory cells that are coupled between the selection transistors; and
a control circuit configured to:
perform a first pre-program operation on a plurality of selection transistors that are included in the plurality of strings, and
sequentially perform an erase operation, a second pre-program operation, a slow transistor masking operation, and a fine program operation on target selection transistors among the plurality of selection transistors.
18 . The memory device according to claim 17 , wherein the second pre-program operation comprises applying a program voltage to the target selection transistors a predetermined number of times while increasing the program voltage incrementally.
19 . The memory device according to claim 18 , wherein the slow transistor masking operation comprises:
verifying threshold voltages of the target selection transistors by using a first verification voltage; and
masking slow transistors, among the target selection transistors, by treating each of the slow transistors as a pass transistor.
20 . The memory device according to claim 19 , wherein the fine program operation comprises:
a first process of applying the program voltage to the target selection transistors;
a second process of verifying threshold voltages of the target selection transistors by using a second verification voltage;
a third process of controlling a program for pass transistors, among the target selection transistors, so that the program is prohibited; and
a fourth process of repeating the first process, the second process, and the third process while increasing the program voltage incrementally until a fail count for the target selection transistors is less than a reference fail count.
21 . The memory device according to claim 20 , wherein the pass transistors comprise a selection transistor having a threshold voltage that is lower than the first verification voltage, among the target selection transistors, and a selection transistor having a threshold voltage that is higher than the second verification voltage, among the target selection transistors.
22 . The memory device according to claim 20 , wherein the control circuit further configured to:
determine new target selection transistors when the fail count is less than the reference fail count; and
sequentially perform the erase operation, the second pre-program operation, the slow transistor masking operation, and the fine program operation on the new target selection transistors.