Semiconductor memory device

1 . A semiconductor memory device comprising:

a first memory cell;

a second memory cell;

a word line that is connected to the first memory cell and the second memory cell;

a first bit line that is connected to the first memory cell;

a second bit line that is connected to the second memory cell;

a first sense amplifier that includes a first node and that is connectable to the first bit line; and

a second sense amplifier that includes a second node and that is connectable to the second bit line, wherein

the semiconductor memory device is configured to execute a writing operation on the first memory cell and the second memory cell, the writing operation including a program operation and a verifying operation,

in a first period of the verifying operation,

the first sense amplifier executes a first sensing operation for determining whether a threshold voltage of the first memory cell is equal to or higher than a first voltage level, and

the second sense amplifier executes a second sensing operation for determining whether a threshold voltage of the second memory cell is equal to or higher than the first voltage level, and

in a second period of the verifying operation following the first period, the first and second sense amplifiers concurrently execute third and fourth sensing operations, respectively,

the third sensing operation being executed to determine whether the threshold voltage of the first memory cell is equal to or higher than a second voltage level that is higher than the first voltage level, and

the fourth sensing operation being executed to determine whether the threshold voltage of the second memory cell is equal to or higher than a third voltage level that is lower than the first voltage level.

2 . The semiconductor memory device of claim 1 , wherein

the first sense amplifier executes the third sensing operation in response to determining, by the first sensing operation, that the threshold voltage of the first memory cell is equal to or higher than the first voltage level, and

the second sense amplifier executes the fourth sensing operation in response to determining, by the second sensing operation, that the threshold voltage of the second memory cell is lower than the first voltage level.

3 . The semiconductor memory device of claim 1 , wherein a duration of discharging electric charges in the first node during the third sensing operation is identical to a duration of discharging electric charges in the second node during the fourth sensing operation.

4 . The semiconductor memory device of claim 3 , wherein

in the first sensing operation and the third sensing operation, the first sense amplifier charges the first node to a first capacitance value,

in the second sensing operation, the second sense amplifier charges the second node to the first capacitance value, and

in the fourth sensing operation, the second sense amplifier charges the second node to a second capacitance value that is larger than the first capacitance value.

5 . The semiconductor memory device of claim 4 , wherein

in response to determining that the threshold voltage of the first memory cell is equal to or higher than the first voltage level, the first sense amplifier charges the first node in the third sensing operation to the first capacitance value, and

in response to determining that the threshold voltage of the second memory cell is lower than the first voltage level, the second sense amplifier charges the second node in the fourth sensing operation to the second capacitance value.

6 . The semiconductor memory device of claim 1 , wherein

in the program operation subsequent to the verifying operation,

in response to determining that the threshold voltage of the first memory cell is lower than the third voltage level, the first sense amplifier applies a second voltage to the first bit line,

in response to determining that the threshold voltage of the first memory cell is equal to or higher than the third voltage level and lower than the first voltage level, the first sense amplifier applies a third voltage that is higher than the second voltage to the first bit line,

in response to determining that the threshold voltage of the second memory cell is equal to or higher than the first voltage level and lower than the second voltage level, the second sense amplifier applies a fourth voltage that is higher than the third voltage to the second bit line, and

in response to determining that the threshold voltage of the second memory cell is equal to or higher than the second voltage level, the second sense amplifier applies a fifth voltage that is higher than the fourth voltage to the second bit line.

7 . A method of performing a write operation in a semiconductor memory device that includes:

a memory cell;

a bit line that is connected to the memory cell; and

a sense amplifier including a sense node that is connectable to the bit line and a latch circuit,

wherein the writing operation includes a program operation and a verifying operation and said method comprises:

in a first period of the verifying operation performed after executing a program operation on the memory cell, executing a first sensing operation by the sense amplifier to determine whether a threshold voltage of the memory cell is equal to or higher than a first voltage level, and storing a result of the first sensing operation in the latch circuit; and

in a second period of the verifying operation following the first period, executing by the sense amplifier a second sensing operation to determine whether the threshold voltage of the memory cell is equal to or higher than a second voltage level that is higher than the first voltage level or a third sensing operation for determining whether the threshold voltage of the memory cell is equal to or higher than a third voltage level that is lower than the first voltage level,

wherein the sense amplifier executes the second sensing operation when the result of the first sensing operation stored in the latch circuit indicates that the threshold voltage of the memory cell is equal to or higher than the first voltage level, and the sense amplifier executes the third sensing operation when the result of the first sensing operation stored in the latch circuit indicates that the threshold voltage of the memory cell is lower than the first voltage level.

8 . The method of claim 7 , wherein

the sense amplifier further includes a first capacitive element that is connected to the sense node and a second capacitive element, and

said method further comprises connecting the second capacitive element to the sense node based on the result of the first sensing operation stored in the latch circuit.

9 . The method of claim 8 , wherein the second capacitive element is not connected to the sense node during the first and second sensing operations and is connected to the sense node during the third sensing operation.

10 . The method of claim 8 , wherein

after connecting the second capacitive element to the sense node, the first capacitive element and the second capacitive element are connected to the sense node in parallel.

11 . The method of claim 8 , wherein

after connecting the second capacitive element to the sense node, the first capacitive element and the second capacitive element are connected to the sense node in series.