IP Library › Granted Patent US 12700462
Granted Patent B2
US 12700462 · App. 18/775,119 · Granted Aug 4, 2026

Semiconductor device

Inventors: Shinya Okuno (Yokohama, JP); Shigeki Nagasaka (Kawasaki, JP); Toshiyuki Kouchi (Kawasaki, JP)
Assignee: KIOXIA CORPORATION
G11C16/32G06F5/06G06F13/1673G11C7/02G11C7/1012G11C7/1039G11C7/106G11C7/1066G11C16/10G11C16/12G11C16/16G11C16/26G06F2205/067G11C16/0483G11C2207/108G11C2207/2281Y02D10/00
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Quick Facts
Patent No.
US 12700462
App. No.
18/775,119
Granted
Aug 4, 2026
Kind
B2
Abstract

A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.

Claims (41)

1 . A semiconductor device comprising:

a memory circuit configured to output data;

a first FIFO configured to receive data from the memory circuit, and output data synchronously with a first clock signal;

a second FIFO configured to receive data output from the first FIFO, and output data synchronously with the first clock signal;

a third FIFO configured to receive data output from the first FIFO, and output data synchronously with the first clock signal;

a signal circuit configured to receive the first clock signal;

a first input/output circuit configured to output first data output from the second FIFO; and

a second input/output circuit configured to output second data output from the third FIFO,

wherein the signal circuit includes a pad sandwiched by the first input/output circuit and the second input/output circuit in a first direction.

2 . The semiconductor device of claim 1 , wherein

the second FIFO is disposed between the first FIFO and the first input/output circuit, and the third FIFO is disposed between the first FIFO and the second input/output circuit.

3 . The semiconductor device of claim 1 , wherein

the second FIFO is located closer to a side of the first input/output circuit than a middle point of an interconnect line connected between the first FIFO and the first input/output circuit, and

the third FIFO is located closer to a side of the second input/output circuit than a middle point of an interconnect line connected between the first FIFO and the second input/output circuit.

4 . The semiconductor device of claim 1 , wherein

a data holding capacity of the second FIFO is lower than a data holding capacity of the first FIFO, and

a data holding capacity of the third FIFO is lower than the data holding capacity of the first FIFO.

5 . The semiconductor device according to claim 1 , wherein data output from the first and second input/output circuits are synchronized with a second clock signal,

further comprising a frequency division circuit frequency-dividing the second clock signal, and generating the first clock signal.

6 . The semiconductor device according to claim 5 , further comprising

a multiplexer disposed between the second FIFO and the first input/output circuit, the multiplexer outputting data at a rise and fall of the second clock signal.

7 . The semiconductor device according to claim 1 , further comprising:

a first semiconductor chip including the memory circuit, and

a second semiconductor chip including the first FIFO, the second FIFO, the third FIFO, the signal circuit, the first input/output circuit, and the second input/output circuit.

8 . The semiconductor device according to claim 7 , wherein

the first semiconductor chip includes a first via which conducts from an upper surface to a lower surface thereof,

the first via and the second semiconductor chip are connected to each other by a first bump, and

data output from the first semiconductor chip is input to the first FIFO of the second semiconductor chip via the first via and the first bump.

9 . The semiconductor device of claim 8 , further comprising

a third semiconductor chip which outputs data,

wherein the first FIFO receives data from the third semiconductor chip, and outputs data synchronously with the first clock signal.

10 . The semiconductor device of claim 9 , wherein

the third semiconductor chip is disposed on the first semiconductor chip and includes a second via which conducts from an upper surface to a lower surface thereof,

the second via and the first via are connected to each other by a second bump, and

data output from the third semiconductor chip is input to the first FIFO of the second semiconductor chip via the second via, the second bump, the first via, and the first bump.

11 . The semiconductor device of claim 9 , wherein

a bus width between the third semiconductor chip and the first FIFO is the same as a bus width between the first FIFO and the second FIFO.

12 . The semiconductor device of claim 7 , wherein

a bus width between the first semiconductor chip and the first FIFO is the same as a bus width between the first FIFO and the second FIFO.

13 . The semiconductor device of claim 7 , wherein

each of the second FIFO and the third FIFO receives, in a divided form, at least part of data output from the first FIFO, and outputs the received data from the first input/output circuit and the second input/output circuit synchronously with the first clock signal.