IP Library › Granted Patent US 12700463
Granted Patent B2
US 12700463 · App. 18/804,617 · Granted Aug 4, 2026

Memory device, memory system, and operating method of memory device

Inventors: Tongsung Kim (Suwon-si, KR); Seonkyoo Lee (Suwon-si, KR); Younggyu Lee (Suwon-si, KR); Taesung Lee (Suwon-si, KR)
Assignee: Samsung Electronics Co., Ltd.
G11C16/32H03K5/1565G11C16/0483G11C16/10G11C16/26
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12700463
App. No.
18/804,617
Granted
Aug 4, 2026
Kind
B2
Abstract

Provided is a memory device including a first pad configured to receive a read enable signal from a memory controller, a second pad configured to receive a read duty cycle correct command signal, a first duty correction circuit configured to perform a read duty cycle correct operation, based on the read duty cycle correct command received from the memory controller, when the read enable signal is received, and output a data strobe signal generated based on the read duty cycle correct operation, and a second duty correction circuit configured to receive the data strobe signal from the first duty correction circuit, generate a divided data strobe signal by dividing the received data strobe signal, and compare the received data strobe signal with the divided data strobe signal to perform a write duty cycle correct operation.

Claims (52)

1 . A memory device comprising:

a first pad configured to receive a read enable signal from a memory controller;

a second pad configured to receive a read duty cycle correct command signal;

a first duty correction circuit configured to perform a read duty cycle correct operation, based on the read duty cycle correct command signal received from the memory controller, when the read enable signal is received, and output a data strobe signal generated based on the read duty cycle correct operation; and

a second duty correction circuit configured to receive the data strobe signal from the first duty correction circuit and generate a divided data strobe signal by dividing the received data strobe signal,

wherein the second duty correction circuit is further configured to divide the received data strobe signal, based on preset criteria, correct a first duty between a first rising edge and a second falling edge of the divided data strobe signal, and correct a second duty between a first falling edge and the second falling edge of the divided data strobe signal.

2 . The memory device of claim 1 , wherein the second duty correction circuit comprises:

a first corrector configured to correct a duty cycle of the divided data strobe signal, based on a first duty cycle ratio between the first rising edge and a second rising edge of the received data strobe signal; and

a second corrector configured to correct the duty cycle of the divided data strobe signal, based on a second duty cycle ratio between the first falling edge and the second falling edge of the received data strobe signal.

3 . The memory device of claim 2 , wherein the second duty correction circuit further comprises:

a third pad configured to receive the data strobe signal from the first duty correction circuit; and

a divider configured to divide the received data strobe signal.

4 . The memory device of claim 2 , wherein the second duty correction circuit further comprises a buffer configured to receive the data strobe signal from the first duty correction circuit, and the second duty correction circuit is further configured to correct the duty cycle of the divided data strobe signal when the buffer is activated.

5 . The memory device of claim 2 , wherein the second duty correction circuit is further configured to divide the received data strobe signal during the read duty cycle correct operation performed in the first duty correction circuit.

6 . The memory device of claim 1 , wherein the second duty correction circuit is further configured to correct a duty cycle of the divided data strobe signal during the read duty cycle correct operation.

7 . The memory device of claim 1 , further comprising a plurality of dies each including the first duty correction circuit and the second duty correction circuit,

wherein the second duty correction circuit included in each of the plurality of dies is configured to receive as an input a data strobe signal output from the first duty correction circuit of at least one of the plurality of dies.

8 . The memory device of claim 1 , wherein the first duty correction circuit comprises a short path switch directly connected to the data strobe signal of the second duty correction circuit.

9 . An operating method of a memory device, the method comprising:

receiving a read duty cycle correct command and a read enable signal from a memory controller;

when the read enable signal is received, performing a read duty cycle correct operation, based on the read duty cycle correct command, and outputting a data strobe signal, based on the read duty cycle correct operation; and

receiving the output data strobe signal, dividing the received data strobe signal, and performing a write duty cycle correct operation,

wherein the performing of the write duty cycle correct operation comprises dividing the data strobe signal, based on preset criteria, and correcting a duty cycle of the divided data strobe signal, based on a first rising edge and a first falling edge of the received data strobe signal.

10 . The operating method of claim 9 , wherein the performing of the write duty cycle correct operation comprises:

correcting the duty cycle of the divided data strobe signal, based on a first duty cycle ratio between the first rising edge and a second rising edge of the received data strobe signal; and

correcting the duty cycle of the divided data strobe signal, based on a second duty cycle ratio between a first falling edge and a second falling edge of the received data strobe signal.

11 . The operating method of claim 9 , wherein the performing of the write duty cycle correct operation further comprises:

receiving the output data strobe signal through a third pad; and

correcting a duty cycle of the data strobe signal received through the third pad.

12 . The operating method of claim 9 , wherein the performing of the write duty cycle correct operation further comprises correcting the duty cycle of the divided data strobe signal when a buffer configured to receive the output data strobe signal is activated.

13 . A memory system comprising:

a memory controller configured to generate a read duty cycle correct command and a read enable signal; and

a memory device configured to perform a training operation with respect to a read signal and a write signal,

wherein the memory device comprises:

a first pad configured to receive the read enable signal from the memory controller;

a second pad configured to receive a read duty cycle correct command signal;

a first duty correction circuit configured to perform a read duty cycle correct operation, based on the read duty cycle correct command signal received from the memory controller, when the read enable signal is received, and output a data strobe signal, based on the read duty cycle correct operation; and

a second duty correction circuit configured to receive the data strobe signal from the first duty correction circuit and generate a divided data strobe signal by dividing the received data strobe signal,

wherein the second duty correction circuit is further configured to divide the received data strobe signal, based on preset criteria, correct a first duty between a first rising edge and a second falling edge of the divided data strobe signal, and correct a second duty between a first falling edge and the second falling edge of the divided data strobe signal.

14 . The memory system of claim 13 , wherein the second duty correction circuit comprises:

a first corrector configured to correct a duty cycle of the divided data strobe signal, based on a first duty cycle ratio between the first rising edge and a second rising edge of the received data strobe signal; and

a second corrector configured to correct the duty cycle of the divided data strobe signal, based on a second duty cycle ratio between the first falling edge and the second falling edge of the received data strobe signal.

15 . The memory system of claim 13 , wherein the second duty correction circuit further comprises:

a third pad configured to receive the output data strobe signal; and

a divider configured to divide the received data strobe signal.

16 . The memory system of claim 13 , wherein the second duty correction circuit further comprises a buffer configured to receive the output data strobe signal, and

wherein the second duty correction circuit is configured to correct a duty cycle of the divided data strobe signal when the buffer is activated.

17 . The memory system of claim 13 , wherein the second duty correction circuit is further configured to divide the received data strobe signal during the read duty cycle correct operation performed in the first duty correction circuit.

18 . The memory system of claim 13 , wherein the second duty correction circuit is further configured to correct a duty cycle of the divided data strobe signal during the read duty cycle correct operation.

19 . The memory system of claim 13 , further comprising a plurality of dies each including the first duty correction circuit and the second duty correction circuit,

wherein the second duty correction circuit included in each of the plurality of dies is configured to receive as an input a data strobe signal output from the first duty correction circuit of at least one of the plurality of dies.

20 . The memory system of claim 13 , wherein the first duty correction circuit comprises a short path switch directly connected to the data strobe signal of the second duty correction circuit.