IP Library › Granted Patent US 12700464
Granted Patent B2
US 12700464 · App. 18/438,636 · Granted Aug 4, 2026

Semiconductor memory device

Inventor: Hiroshi Maejima (Tokyo, JP)
Assignee: Kioxia Corporation
G11C16/3427G11C16/0483G11C16/08G11C16/10G11C16/26H10B80/00H10W90/00H10W90/792
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12700464
App. No.
18/438,636
Granted
Aug 4, 2026
Kind
B2
Abstract

According to one embodiment, a semiconductor memory device includes, a first string in which a first selection transistor, a first memory cell, and a second selection transistor are coupled in series, a second string in which a third selection transistor, a second memory cell, and a fourth selection transistor are coupled in series, a word line, a first selection gate line, a second selection gate line, a third selection gate line, a fourth selection gate line, a first bit line, and a second bit line. In a read operation of the first memory cell, when a voltage of the word line is raised to a first voltage, a second voltage is applied to the first bit line and a third voltage higher than the second voltage is applied to the second bit line.

Claims (84)

1 . A semiconductor memory device, comprising:

a first string in which a first selection transistor, a first memory cell, and a second selection transistor are coupled in series;

a second string in which a third selection transistor, a second memory cell, and a fourth selection transistor are coupled in series;

a word line coupled to a gate of the first memory cell and a gate of the second memory cell;

a first selection gate line coupled to a gate of the first selection transistor;

a second selection gate line coupled to a gate of the second selection transistor;

a third selection gate line coupled to a gate of the third selection transistor;

a fourth selection gate line coupled to a gate of the fourth selection transistor;

a first bit line coupled to the first selection transistor; and

a second bit line coupled to the third selection transistor,

wherein

in a read operation of the first memory cell, when a voltage of the word line is raised to a first voltage, a second voltage is applied to the first bit line and a third voltage higher than the second voltage is applied to the second bit line, the first selection transistor, the second selection transistor, and the third selection transistor are turned on, and the fourth selection transistor is turned off, and

the third selection transistor is turned off when data is read from the first memory cell after the voltage of the word line is raised to the first voltage.

2 . The semiconductor memory device according to claim 1 , wherein

in the read operation of the first memory cell, a read voltage lower than the first voltage is applied to the word line when data is read from the first memory cell after the voltage of the word line is raised to the first voltage.

3 . The semiconductor memory device according to claim 1 , further comprising:

a row decoder coupled to the word line, the first selection gate line, the second selection gate line, the third selection gate line, and the fourth selection gate line; and

a sense amplifier coupled to the first bit line and the second bit line.

4 . The semiconductor memory device according to claim 1 , wherein

the write operation includes a program loop that alternately repeats a program operation and a program verify operation, and

in the program operation of the first memory cell, when the voltage of the word line is raised to a fourth voltage, a fifth voltage is applied to the first bit line and a sixth voltage higher than the fifth voltage is applied to the second bit line.

5 . A semiconductor memory device comprising:

a first string in which a first selection transistor, a first memory cell, and a second selection transistor are coupled in series;

a second string in which a third selection transistor, a second memory cell, and a fourth selection transistor are coupled in series;

a word line coupled to a gate of the first memory cell and a gate of the second memory cell;

a first selection gate line coupled to a gate of the first selection transistor;

a second selection gate line coupled to a gate of the second selection transistor;

a third selection gate line coupled to a gate of the third selection transistor;

a fourth selection gate line coupled to a gate of the fourth selection transistor;

a first bit line coupled to the first selection transistor; and

a second bit line coupled to the third selection transistor,

wherein

in a read operation of the first memory cell, when a voltage of the word line is raised to a first voltage, a second voltage is applied to the first bit line and a third voltage higher than the second voltage is applied to the second bit line,

the write operation includes a program loop that alternately repeats a program operation and a program verify operation,

in the program operation of the first memory cell, when the voltage of the word line is raised to a fourth voltage, a fifth voltage is applied to the first bit line, a sixth voltage higher than the fifth voltage is applied to the second bit line, the first selection transistor and the third selection transistor are turned on, and the second selection transistor and the fourth selection transistor are turned off.

6 . The semiconductor memory device according to claim 5 , wherein

in the program operation of the first memory cell, after the voltage of the word line is raised to the fourth voltage, a program voltage higher than the fourth voltage is applied to the word line.

7 . The semiconductor memory device according to claim 6 , wherein

in the program operation of the first memory cell, the third selection transistor is turned off while the program voltage is applied to the word line.

8 . A semiconductor memory device, comprising:

a first string in which a first selection transistor, a first memory cell, and a second selection transistor are coupled in series;

a second string in which a third selection transistor, a second memory cell, and a fourth selection transistor are coupled in series;

a word line coupled to a gate of the first memory cell and a gate of the second memory cell;

a first selection gate line coupled to a gate of the first selection transistor;

a second selection gate line coupled to a gate of the second selection transistor;

a third selection gate line coupled to a gate of the third selection transistor;

a fourth selection gate line coupled to a gate of the fourth selection transistor;

a first bit line coupled to the first selection transistor;

a second bit line coupled to the third selection transistor;

a first source line coupled to the second selection transistor; and

a second source line coupled to the fourth selection transistor,

wherein

in a read operation of the first memory cell, when a voltage of the word line is raised to a first voltage, a second voltage is applied to the first source line, a third voltage higher than the second voltage is applied to the second source line, the first selection transistor and the third selection transistor are turned off, and the second selection transistor and the fourth selection transistor are turned on, and

after the voltage of the word line is raised to the first voltage, when data is read from the first memory cell, the first selection transistor is turned on, and the fourth selection transistor is turned off.

9 . The semiconductor memory device according to claim 8 , wherein

in the read operation of the first memory cell, a read voltage lower than the first voltage is applied to the word line when data is read from the first memory cell after the voltage of the word line is raised to the first voltage.

10 . The semiconductor memory device according to claim 8 , further comprising:

a row decoder coupled to the word line, the first selection gate line, the second selection gate line, the third selection gate line, and the fourth selection gate line;

a sense amplifier coupled to the first bit line and the second bit line; and

a source line driver coupled to the first source line and the second source line.

11 . The semiconductor memory device according to claim 8 , wherein

the write operation includes a program loop that alternately repeats a program operation and a program verify operation, and

in the program operation of the first memory cell, when the voltage of the word line is raised to a fourth voltage, a fifth voltage is applied to the first source line, and a sixth voltage higher than the fifth voltage is applied to the second source line.

12 . The semiconductor memory device according to claim 11 , wherein

in the program operation of the first memory cell, after the voltage of the word line is raised to the fourth voltage, a program voltage higher than the fourth voltage is applied to the word line.

13 . The semiconductor memory device according to claim 12 , wherein

the second selection transistor and the fourth selection transistor are turned off during a period in which the program voltage is applied to the word line.

14 . The semiconductor memory device according to claim 8 , wherein

in the read operation of the first memory cell, a seventh voltage is applied to the first bit line and an eighth voltage higher than the seventh voltage is applied to the second bit line when the voltage of the word line is raised to the first voltage.

15 . The semiconductor memory device according to claim 14 , wherein

in the read operation of the first memory cell, the first selection transistor, the second selection transistor, the third selection transistor, and the fourth selection transistor are turned on when the voltage of the word line is raised to the first voltage, and

the second selection transistor and the fourth selection transistor are turned off when data is read from the first memory cell after the voltage of the word line is raised to the first voltage.

16 . The semiconductor memory device according to claim 14 , wherein

in the read operation of the first memory cell, a read voltage lower than the first voltage is applied to the word line when data is read from the first memory cell after the voltage of the word line is raised to the first voltage.

17 . The semiconductor memory device according to claim 3 , further comprising:

a circuit chip including the row decoder and the sense amplifier;

a first array chip including the first string; and

a second array chip including the second string, wherein

the circuit chip is bonded to a first surface of the first array chip, and the second array chip is bonded to a second surface of the first array chip facing the first surface.

18 . The semiconductor memory device according to claim 10 , further comprising:

a circuit chip including the row decoder and the sense amplifier;

a first array chip including the first string; and

a second array chip including the second string, wherein

the circuit chip is bonded to a first surface of the first array chip, and the second array chip is bonded to a second surface of the first array chip facing the first surface.