IP Library › Granted Patent US 12700465

Granted Patent B2

US 12700465 · App. 18/635,793 · Granted Aug 4, 2026

Memory device, system, and operating method for facilitating programming verification operations

Inventor: Li Xiang (Wuhan, CN)

Assignee: Yangtze Memory Technologies Co., Ltd.

G11C16/3459 G11C16/0433 G11C16/26

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Quick Facts

Patent No.: US 12700465
App. No.: 18/635,793
Granted: Aug 4, 2026
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

The present disclosure provides memory devices, operating methods, memory systems. An example memory device includes a memory array and a peripheral circuit. The memory array includes a first and a second finger memory region, each region including multiple memory cell strings. Each memory cell string includes a first bottom select transistor (BSG). First BSGs in the first and second finger memory regions have a first and a second threshold voltage, respectively. The peripheral circuit is configured to: apply a first bias voltage to the BSGs in the first pre-charge phase of a programming verification operation on the first finger memory region; apply a second bias voltage to the first BSGs after the first pre-charge phase; the first bias voltage is smaller than the second bias voltage; and the second bias voltage is smaller than the second threshold voltage and greater than the first threshold voltage.

Claims (56)

1 . A memory device, comprising a memory array and a peripheral circuit coupled with the memory array, wherein:

the memory array comprises a first finger memory region and a second finger memory region each comprising a plurality of memory cell strings; each of the memory cell strings comprises a first bottom select transistor and a second bottom select transistor; first bottom select transistors in the first finger memory region have a first threshold voltage, first bottom select transistors in the second finger memory region have a second threshold voltage, and the first threshold voltage is smaller than the second threshold voltage; second bottom select transistors in the first finger memory region have a third threshold voltage; and

the peripheral circuit is configured to:

apply a first bias voltage to first bottom select transistors in the first finger memory region in a first pre-charge phase of a programming verification operation on memory cells in the first finger memory region;

apply a second bias voltage to the first bottom select transistors in the first finger memory region in a first sensing phase after the first pre-charge phase, wherein the first bias voltage is smaller than the second bias voltage; and the second bias voltage is smaller than the second threshold voltage and greater than the first threshold voltage; and

apply a first pass voltage greater than the third threshold voltage to the second bottom select transistors in the first finger memory region in the first pre-charge phase and the first sensing phase.

2 . The memory device of claim 1 , wherein second bottom select transistors in the second finger memory region have a fourth threshold voltage, and the third threshold voltage is greater than the fourth threshold voltage; and

wherein apply the first pass voltage greater than the third threshold voltage to the second bottom select transistors comprises:

apply the first pass voltage greater than the third threshold voltage to the second bottom select transistors in the first finger memory region in the first pre-charge phase and the first sensing phase.

3 . The memory device of claim 2 , wherein each of the memory cell strings further comprises a third bottom select transistor, the third bottom select transistor is between the first bottom select transistor and the second bottom select transistor and has a fifth threshold voltage; and

the peripheral circuit is further configured to apply a second pass voltage greater than the fifth threshold voltage to the third bottom select transistor in the first pre-charge phase and the first sensing phase.

4 . The memory device of claim 3 , wherein the first bias voltage is greater than or equal to a negative second pass voltage and the second bias voltage is smaller than the second pass voltage.

5 . The memory device of claim 2 , wherein the memory array further comprises a common source line connected with each of the memory cell strings, each of the memory cell strings further comprises a fourth bottom select transistor, the fourth bottom select transistor is closer to the common source line than the first bottom select transistor and the second bottom select transistor and has a sixth threshold voltage; and

the peripheral circuit is further configured to apply a third pass voltage greater than the sixth threshold voltage to the fourth bottom select transistor in the first pre-charge phase and the first sensing phase.

6 . The memory device of claim 5 , wherein the first bias voltage is greater than or equal to a negative third pass voltage and the second bias voltage is smaller than the third pass voltage.

7 . The memory device of claim 2 , wherein the peripheral circuit is further configured to:

apply a fourth pass voltage greater than the second threshold voltage to the first bottom select transistors in the second finger memory region and apply a third bias voltage to the second bottom select transistors in the second finger memory region in a second pre-charge phase of a programming verification operation on memory cells in the second finger memory region; and

apply the fourth pass voltage to the first bottom select transistors in the second finger memory region and apply a fourth bias voltage to the second bottom select transistors in the second finger memory region in a second sensing phase after the second pre-charge phase, wherein the third bias voltage is smaller than the fourth bias voltage; and the fourth bias voltage is smaller than the third threshold voltage and greater than the fourth threshold voltage.

8 . The memory device of claim 1 , wherein each of the memory cell strings further comprises a top select transistor; and the peripheral circuit is further configured to:

turn on top select transistors in the first finger memory region in the first pre-charge phase;

turn off unselected top select transistors in the first finger memory region and turn on selected top select transistors in the first finger memory region in the first sensing phase; and

turn off top select transistors in the second finger memory region in the first pre-charge phase and the first sensing phase.

9 . A memory system, comprising:

at least one memory device, each of the at least one memory device comprises a memory array and a peripheral circuit coupled with the memory array, wherein:

the memory array comprises a first finger memory region and a second finger memory region each comprising a plurality of memory cell strings, each of the memory cell strings comprises a first bottom select transistor and a second bottom select transistor, first bottom select transistors in the first finger memory region have a first threshold voltage, first bottom select transistors in the second finger memory region have a second threshold voltage, and the first threshold voltage is smaller than the second threshold voltage; second bottom select transistors in the first finger memory region have a third threshold voltage; and

the peripheral circuit is configured to:

apply a second bias voltage to the first bottom select transistors in the first finger memory region in a first sensing phase after the first pre-charge phase; wherein the first bias voltage is smaller than the second bias voltage; and the second bias voltage is smaller than the second threshold voltage and greater than the first threshold voltage; and

a controller coupled with the at least one memory device and configured to control the at least one memory device.

10 . The memory system of claim 9 , wherein second bottom select transistors in the second finger memory region have a fourth threshold voltage, and the third threshold voltage is greater than the fourth threshold voltage; and

wherein apply the first pass voltage greater than the third threshold voltage to the second bottom select transistors comprises:

11 . The memory device of claim 10 , wherein each of the memory cell strings further comprises a third bottom select transistor, the third bottom select transistor is between the first bottom select transistor and the second bottom select transistor and has a fifth threshold voltage; and

12 . The memory device of claim 11 , wherein the first bias voltage is greater than or equal to a negative second pass voltage and the second bias voltage is smaller than the second pass voltage.

13 . A operating method of a memory device, comprising:

applying a first bias voltage to a first bottom select transistor in each of memory cell strings in a first pre-charge phase of a programming verification operation on memory cells in a first finger memory region of a memory device, wherein each of the memory cell strings comprises a first bottom select transistor and a second bottom select transistor, and wherein second bottom select transistors in the first finger memory region have a third threshold voltage;

applying a second bias voltage to the first bottom select transistor in a first sensing phase after the first pre-charge phase, wherein the first bias voltage is smaller than the second bias voltage; and the second bias voltage is smaller than a second threshold voltage of first bottom select transistors in a second finger memory region of the memory device and greater than a first threshold voltage of first bottom select transistors in the first finger memory region of the memory device; and

applying a first pass voltage greater than a third threshold voltage to second bottom select transistors in the first finger memory region in the first pre-charge phase and the first sensing phase.

14 . The operating method of the memory device of claim 13 , wherein apply the first pass voltage greater than the third threshold voltage to the second bottom select transistors comprises:

applying the first pass voltage to a second bottom select transistor in each of the memory cell strings in the first pre-charge phase and the first sensing phase, wherein the third threshold voltage is greater than a fourth threshold voltage of second bottom select transistors in the second finger memory region.

15 . The operating method of the memory device of claim 14 , further comprising:

applying a second pass voltage to a third bottom select transistor between the first bottom select transistor and the second bottom select transistor in the first pre-charge phase and the first sensing phase, wherein the second pass voltage is greater than a fifth threshold voltage of the third bottom select transistor.

16 . The operating method of the memory device of claim 15 , wherein the first bias voltage is greater than or equal to a negative second pass voltage and the second bias voltage is smaller than the second pass voltage.

17 . The operating method of the memory device of claim 14 , further comprising:

applying a third pass voltage to a fourth bottom select transistor closer to a common source line than the first bottom select transistor and the second bottom select transistor in the first pre-charge phase and the first sensing phase, wherein the third pass voltage is greater than a sixth threshold voltage of the fourth bottom select transistor.

18 . The operating method of the memory device of claim 17 , wherein the first bias voltage is greater than or equal to a negative third pass voltage and the second bias voltage is smaller than the third pass voltage.

19 . The operating method of the memory device of claim 14 , further comprising:

applying a fourth pass voltage greater than the second threshold voltage to the first bottom select transistor; and

applying a third bias voltage to the second bottom select transistor in a second pre-charge phase of a programming verification on the memory cells in the second finger memory region; and

applying the fourth pass voltage to the first bottom select transistor and applying a fourth bias voltage to the second bottom select transistor in a second sensing phase after the second pre-charge phase, wherein the third bias voltage is smaller than the fourth bias voltage; and the fourth bias voltage is smaller than the third threshold voltage and greater than the fourth threshold voltage.

20 . The operating method of the memory device of claim 13 , further comprising:

turning on top select transistors in the first finger memory region in the first pre-charge phase;

turning off unselected top select transistors in the first finger memory region and turning on selected top select transistors in the first finger memory region in the first sensing phase; and

turning off top select transistors in the second finger memory region in the first pre-charge phase and the first sensing phase.