One-time programmable memory devices with heater devices and methods for manufacturing and operating the same
View Patent ↗A semiconductor device includes a memory cell including a first transistor, a second transistor, and a resistor. Each of the first transistor and the second transistor is operatively coupled to the resistor in series. The second transistor is formed below the resistor such that the second transistor provides heat to the resistor when the memory cell is being programmed.
1 . A semiconductor device, comprising:
a memory cell including a first transistor, a second transistor, and a resistor;
wherein each of the first transistor and the second transistor is operatively coupled to the resistor in series; and
wherein the second transistor is physically formed over one or more dielectric layers such that the second transistor is configured to operatively accumulate heat blocked by the one or more dielectric layers, and configured to provide the accumulated heat to the resistor when the memory cell is being programmed.
2 . The semiconductor device of claim 1 , wherein the first transistor and the second transistor are both formed in a front-end-of-line (FEOL) network over a semiconductor substrate, and the resistor is formed in a back-end-of-line (BEOL) network over the FEOL network.
3 . The semiconductor device of claim 2 , wherein the first transistor includes a plurality of first channel structures vertically spaced from one another and a pair of first source/drain structures, and the second transistor includes a plurality of second channel structures vertically spaced from one another and pair of second source/drain structures.
4 . The semiconductor device of claim 3 , wherein the pair of second source/drain structures are physically disposed above the semiconductor substrate through the one or more dielectric layers.
5 . The semiconductor device of claim 3 , wherein the second channel structures and the pair of second source/drain structures are physically disposed above the semiconductor substrate through the one or more dielectric layers.
6 . The semiconductor device of claim 3 , wherein the second transistor is disposed directly below the resistor, while the first transistor is disposed laterally next to the second transistor.
7 . The semiconductor device of claim 1 , wherein the first transistor is formed in a front-end-of-line (FEOL) network over a semiconductor substrate, the second transistor and the resistor are formed in a back-end-of-line (BEOL) network over the FEOL network.
8 . The semiconductor device of claim 7 , wherein the second transistor includes a two-dimensional channel formed of a semiconductive-behaving oxide material.
9 . The semiconductor device of claim 1 , wherein the first transistor, the second transistor, and the resistor are formed in a back-end-of-line (BEOL) network over a front-end-of-line (FEOL) network over a semiconductor substrate.
10 . The semiconductor device of claim 9 , wherein the first transistor includes a three-dimensional channel formed of a first semiconductive-behaving oxide material, the second transistor includes a two-dimensional channel formed of a second semiconductive-behaving oxide material.
11 . The semiconductor device of claim 1 , wherein the memory cell includes an electrical fuse configured to be programmed once.
12 . A method for forming memory devices, comprising:
forming a plurality of front-end-of-line (FEOL) transistors along a frontside surface of a substrate;
forming one or more dielectric layers along the frontside surface of the substrate; and
forming a metal resistor in a first one of a plurality of metallization layers that are disposed over the frontside surface of the substrate;
wherein a first one of the FEOL transistors is electrically coupled to the metal resistor, and wherein a second one of the FEOL transistors is configured to accumulate heat with the one or more dielectric layer and thermally coupled to the metal resistor.
13 . The method of claim 12 , wherein the second FEOL transistor is formed over one or more dielectric layers that are interposed between the substrate and the second FEOL transistor such that the second FEOL transistor is configured to accumulate heat and provide the accumulated heat to the metal resistor.
14 . A semiconductor device, comprising:
a memory cell including a first transistor, a second transistor, and a resistor;
wherein each of the first transistor and the second transistor is operatively coupled to the resistor in series; and
wherein the first transistor are the second transistor are both formed over a semiconductor substrate, and wherein one or more dielectric layers are disposed between the semiconductor substrate and only the second transistor, causing the second transistor to accumulate heat using the one or more dielectric layers.
15 . The semiconductor device of claim 14 , wherein the first transistor and the second transistor are both formed in a front-end-of-line (FEOL) network over the semiconductor substrate, and the resistor is formed in a back-end-of-line (BEOL) network over the FEOL network.
16 . The semiconductor device of claim 14 , wherein the second transistor is configured to provide the accumulated heat to the resistor when the memory cell is being programmed.
17 . The semiconductor device of claim 14 , wherein the first transistor includes a plurality of first channel structures vertically spaced from one another and a pair of first source/drain structures, and the second transistor includes a plurality of second channel structures vertically spaced from one another and pair of second source/drain structures.
18 . The semiconductor device of claim 17 , wherein at least one of the second channel structures or the pair of second source/drain structures are directly disposed above the one or more dielectric layers.
19 . The semiconductor device of claim 14 , wherein the second transistor is disposed directly below the resistor, while the first transistor is disposed laterally next to the second transistor.
20 . The semiconductor device of claim 14 , wherein the memory cell includes an electrical fuse configured to be programmed once.
21 . The semiconductor device of claim 14 , wherein the one or more dielectric layers each include silicon germanium oxide (SiGeO x ) and/or germanium oxide (GeO x ).