Secure anti-fuse one time programmable bit cell design
Disclosed are secure anti-fuse one-time programmable (OTP) bit cells. In an aspect, an OTP bit cell includes a P− well comprising an N+ region and a P+ region, a first contact electrically coupled to the N+ region of the P− well, a second contact electrically coupled to the P+ region of the P− well, an insulating layer disposed over a portion of the N+ region, a portion of the P− well, and a portion of the P+ region, a gate structure disposed over the insulating layer, and a third contact electrically coupled to the gate structure. In an unprogrammed mode, the insulating layer creates a high resistance between the third contact and the second contact, and in a programmed mode, a rupture in the insulating layer creates a low resistance between the third contact and the second contact.
1 . A one-time programmable (OTP) bit cell, comprising:
a P-well comprising an N+ region and a P+ region;
a first contact electrically coupled to the N+ region of the P−well;
a second contact electrically coupled to the P+ region of the P−well;
an insulating layer disposed over a portion of the N+ region, a portion of the P-well, and a portion of the P+ region;
a gate structure disposed over the insulating layer and comprising a P+ region adjacent to the insulating layer and opposite the insulating layer from at least a portion of the N+ region of the P− well; and
a third contact electrically coupled to the gate structure,
wherein the P− well is disposed above an insulating layer comprising a buried oxide (BOX) layer or shallow trench isolation (STI) structure.
2 . The OTP bit cell of claim 1 , wherein the insulating layer comprises a silicon dioxide (SiO2) layer.
3 . The OTP bit cell of claim 1 , wherein the P+ region of the gate structure comprises P+ polysilicon.
4 . The OTP bit cell of claim 3 , wherein the gate structure further comprises a silicide layer disposed between the P+ polysilicon and the third contact.
5 . The OTP bit cell of claim 1 , wherein the first contact is a programming lead, the second contact is a reading lead, and the third contact is a gate contact.
6 . A one-time programmable (OTP) bit cell, comprising:
a first substrate layer comprising an insulating layer comprising a buried oxide (BOX) layer or a shallow trench isolation (STI) structure;
an insulating layer disposed over the first substrate layer;
a gate structure disposed over the insulating layer and comprising a P+region adjacent to the insulating layer;
a first contact electrically coupled to the gate structure; and
a second contact coupled to the first substrate layer and in direct contact with the insulating layer.
7 . The OTP bit cell of claim 6 , wherein the insulating layer comprises a silicon dioxide (SiO2) layer.
8 . The OTP bit cell of claim 6 , wherein the P+ region of the gate structure comprises P+ polysilicon.
9 . The OTP bit cell of claim 8 , wherein the gate structure further comprises a silicide layer disposed between the P+ polysilicon and the first contact.
10 . The OTP bit cell of claim 6 , wherein the first contact is a gate contact and the second contact is a programming and reading lead.
11 . A method of fabricating a one-time programmable (OTP) bit cell, the method comprising:
providing a P− well comprising an N+ region and a P+ region above an insulating layer comprising a buried oxide (BOX) layer or a shallow trench isolation (STI) structure;
providing a first contact electrically coupled to the N+ region of the P− well;
providing a second contact electrically coupled to the P+ region of the P− well;
providing an insulating layer disposed over a portion of the N+ region, a portion of the P− well, and a portion of the P+ region;
providing a gate structure disposed over the insulating layer and comprising a P+ region adjacent to the insulating layer and opposite the insulating layer from at least a portion of the N+ region of the P− well; and
providing a third contact electrically coupled to the gate structure.
12 . The method of claim 11 , wherein providing the insulating layer comprises providing a silicon dioxide (SiO2) layer.
13 . The method of claim 11 , wherein providing the P+ region of the gate structure comprises providing P+ polysilicon.
14 . The method of claim 13 , wherein providing the gate structure further comprises providing a silicide layer disposed between the P+ polysilicon and the third contact.
15 . A method of fabricating a one-time programmable (OTP) bit cell, the method comprising:
providing a first substrate layer comprising an insulating layer comprising a buried oxide (BOX) layer or a shallow trench isolation (STI) structure;
providing an insulating layer disposed over the first substrate layer;
providing a gate structure disposed over the insulating layer and comprising a P+ region adjacent to the insulating layer;
providing a first contact electrically coupled to the gate structure; and
providing a second contact coupled to the first substrate layer and in direct contact with the insulating layer.
16 . The method of claim 15 , wherein providing the insulating layer comprises providing a silicon dioxide (SiO2) layer.
17 . The method of claim 15 , wherein providing the P+ region of the gate structure comprises providing P+ polysilicon.
18 . The method of claim 17 , wherein providing the gate structure further comprises providing a silicide layer disposed between the P+ polysilicon and the first contact.