Memory device with control elements for unselected defective and unselected non-defective memory blocks
A memory device includes a memory cell array including a block including a first transistor connected to a first select gate line, a second transistor connected to a second select gate line, and a plurality of memory cells connected in series between the first and second transistors and each connected to one corresponding word line of a plurality of word lines, and a row control circuit that outputs a control signal for setting the block to be in a selected state or an unselected state based on a result of decoding an address, stores information indicating whether the block is a non-defective block, and controls an electrical state of the second select gate line independently of the first select gate line based on the control signal and the information.
1 . A memory device comprising:
a memory cell array including a block including:
a first transistor connected to a first select gate line,
a second transistor connected to a second select gate line, and
a plurality of memory cells connected in series between the first transistor and the second transistor and each connected to one corresponding word line of a plurality of word lines; and
a row control circuit configured to:
output a first control signal for setting the block to be in a selected state or an unselected state based on a result of decoding an address,
store information indicating whether the block is a non-defective block or a defective block, and
control an electrical state of the second select gate line independently of the first select gate line based on the first control signal and the information;
wherein when the block is set to be in the unselected state by the first control signal and the information indicates that the block is the non-defective block, the row control circuit sets the second select gate line to be in an electrically floating state, and
when the block is set to be in the unselected state by the first control signal and the information indicates that the block is the defective block, the row control circuit sets the second select gate line to be in an electrically bias state.
2 . The memory device according to claim 1 ,
wherein when the block is set to be in the unselected state by the first control signal and the information indicates that the block is the non-defective block, the row control circuit sets the first select gate line to be in an electrically bias state.
3 . The memory device according to claim 1 ,
wherein a ground voltage is applied to the second select gate line set to be in the bias state.
4 . The memory device according to claim 1 ,
wherein the row control circuit is configured to receive a second control signal for controlling a state of a voltage of the second select gate line,
when a signal level of the second control signal is a first level,
the row control circuit is configured to set the second select gate line to be in an electrically bias state when the block is controlled to be in the unselected state by the first control signal, and
when the signal level of the second control signal is a second level, the row control circuit:
sets the second select gate line to be in an electrically floating state when the block is set to be in the unselected state by the first control signal and the information indicates that the block is the non-defective block, and
sets the second select gate line to be in the electrically bias state when the block is set to be in the unselected state by the first control signal and the information indicates that the block is the defective block.
5 . The memory device according to claim 4 ,
wherein when the block is set to be in the unselected state by the first control signal and the information indicates that the block is the non-defective block, the row control circuit sets the first select gate line to be in an electrically bias state.
6 . The memory device according to claim 4 ,
wherein a ground voltage is applied to the second select gate line set to be in the bias state.
7 . The memory device according to claim 1 , further comprising:
a driver circuit configured to output a plurality of voltages to be applied to the first select gate line, the second select gate line, and the plurality of word lines,
wherein the row control circuit includes:
a decode circuit configured to generate the first control signal,
a latch circuit configured to store the information,
a switch circuit configured to electrically connect or disconnect the block and the driver circuit, and
a switch control circuit configured to control the switch circuit, and
the switch control circuit is configured to control the electrical connection or disconnection between the driver circuit and the second select gate line by the switch circuit, based on the first control signal and the information.
8 . The memory device according to claim 7 ,
wherein the switch control circuit includes:
a NOR gate including a first input node configured to receive the first control signal,
a second input node configured to receive the information, and
a first output node configured to output a first signal indicating a result of a logical NOR operation between the first control signal and the information.
9 . The memory device according to claim 8 ,
wherein the switch circuit includes: a first switch including:
a first terminal connected to the first select gate line,
a second terminal connected to the driver circuit, and
a first gate configured to receive an inverted signal of the first control signal, and
a second switch including:
a third terminal connected to the second select gate line,
a fourth terminal connected to the driver circuit, and
a second gate configured to receive the first signal.
10 . The memory device according to claim 9 ,
wherein the driver circuit includes a driver configured to output a voltage to the first select gate line and the second select gate line of the block in the unselected state, and
the second and fourth terminals are connected to the driver through a wiring.
11 . The memory device according to claim 7 ,
wherein the switch control circuit includes:
a first P-type transistor including:
a first terminal connected to a first power terminal,
a second terminal connected to a first node configured to transfer a signal to the switch circuit, and a first gate configured to receive the first control signal,
a first N-type transistor including a third terminal connected to the first node, a fourth terminal connected to a second power terminal, and a second gate configured to receive the first control signal,
a second P-type transistor including a fifth terminal connected to the first power terminal, a sixth terminal connected to the first terminal, and a third gate configured to receive the information, and
a second N-type transistor including a seventh terminal connected to the first node, an eighth terminal connected to the second power terminal, and a fourth gate configured to receive the information.
12 . The memory device according to claim 7 ,
wherein the row control circuit is configured to receive a second control signal for controlling a state of a voltage of the second select gate line,
the switch control circuit includes:
an AND gate including a first input node configured to receive the information,
a second input node configured to receive the second control signal, and
a first output node configured to output a first signal indicating a result of a logical AND between the information and the second control signal, and
a NOR gate including a third input node configured to receive the first control signal, a fourth input node configured to receive the first signal, and a second output node configured to output a second signal indicating a result of a logical NOR between the first control signal and the first signal.
13 . The memory device according to claim 12 ,
wherein the switch circuit includes:
a first switch including:
a first terminal connected to the first select gate line,
a second terminal connected to the driver circuit, and
a first gate configured to receive an inverted signal of the first control signal, and
a second switch including:
a third terminal connected to the second select gate line,
a fourth terminal connected to the driver circuit, and
a second gate configured to receive the second signal.
14 . The memory device according to claim 13 ,
wherein the driver circuit includes a driver configured to output a voltage to the first select gate line and the second select gate line of the block in the unselected state, and
the second and fourth terminals are connected to the driver through a wiring.
15 . The memory device according to claim 7 ,
wherein the row control circuit is configured to receive a second control signal for controlling a state of a voltage of the second select gate line, and
the row control circuit includes:
a first P-type transistor including a first terminal connected to a first power terminal, a second terminal connected to a first node, and a first gate configured to receive the second control signal,
a second P-type transistor including a third terminal connected to the first node, a fourth terminal connected to a second node for transferring a signal to the switch circuit, and a second gate configured to receive the first control signal,
a first N-type transistor including a fifth terminal connected to the second node, a sixth terminal connected to a second power terminal, and a third gate configured to receive the first control signal,
a third P-type transistor including a seventh terminal connected to the first power terminal, an eighth terminal connected to the first node, and a fourth gate configured to receive the information,
a second N-type transistor including a ninth terminal connected to the second node, a tenth terminal, and a fifth gate configured to receive the information, and
a third N-type transistor including an eleventh terminal connected to the tenth terminal, a twelfth terminal connected to the second power terminal, and a sixth gate configured to receive the second control signal.
16 . The memory device according to claim 1 ,
wherein each of the plurality of memory cells includes:
a semiconductor layer extending in a first direction perpendicular to a surface of a substrate,
a first conductive layer facing the semiconductor layer in a second direction parallel to the surface of the substrate,
a first insulating layer between the first conductive layer and the semiconductor layer,
a second insulating layer between the first conductive layer and the first insulating layer, and
a charge storage layer between the first insulating layer and the second insulating layer.
17 . A memory device comprising:
a memory cell array including a block including:
a first transistor connected to a first select gate line,
a second transistor connected to a second select gate line, and
a plurality of memory cells connected in series between the first transistor and the second transistor and each connected to one corresponding word line of a plurality of word lines; and
a row control circuit including:
a first control circuit configured to control an electrical state of the first select gate line based on a first control signal for setting the block to be in a selected state or an unselected state, and
a second control circuit configured to control an electrical state of the second select gate line based on the first control signal and information indicating whether the block is a non-defective block or a defective block;
wherein the row control circuit is configured to receive a second control signal for controlling a state of a voltage of the second select gate line, and
the row control circuit includes:
a first P-type transistor including a first terminal connected to a first power terminal,
a second terminal connected to a first node, and
a first gate configured to receive the second control signal,
a second P-type transistor including a third terminal connected to the first node, a fourth terminal connected to a second node for transferring a signal to the switch circuit, and a second gate configured to receive the first control signal,
a first N-type transistor including a fifth terminal connected to the second node, a sixth terminal connected to a second power terminal, and a third gate configured to receive the first control signal,
a third P-type transistor including a seventh terminal connected to the first power terminal, an eighth terminal connected to the first node, and a fourth gate configured to receive the information,
a second N-type transistor including a ninth terminal connected to the second node, a tenth terminal, and a fifth gate configured to receive the information, and
a third N-type transistor including an eleventh terminal connected to the tenth terminal, a twelfth terminal connected to the second power terminal, and a sixth gate configured to receive the second control signal.
18 . The memory device according to claim 17 , further comprising:
a driver circuit configured to output a plurality of voltages to be applied to the first select gate line, the second select gate line, and the plurality of word lines,
wherein the row control circuit includes:
a decode circuit configured to generate the first control signal,
a latch circuit configured to store the information,
a switch circuit configured to electrically connect or disconnect the block and the driver circuit, and
a switch control circuit configured to control the switch circuit, and
the switch control circuit is configured to control the electrical connection or disconnection between the driver circuit and the second select gate line by the switch circuit, based on the first control signal and the information.