Memory device and method for calibrating impedance thereof

1 . A memory device comprising:

a memory cell array;

an input/output circuit configured to control inputting of data to the memory cell array and outputting of data stored in the memory cell array;

an impedance calibration circuit configured to generate an impedance calibration code based on an external resistor connected to an impedance pad for application to the input/output circuit as an applied impedance calibration code; and

a calibration control circuit configured to compare a new impedance calibration code received from the impedance calibration circuit with a calibration code range to generate a calibration code update flag when the new impedance calibration code is included in the calibration code range,

wherein the impedance calibration circuit is configured to update the applied impedance calibration code with the new impedance calibration code when receiving the calibration code update flag.

2 . The memory device of claim 1 , wherein the impedance calibration circuit is configured to discard the new impedance calibration code and maintain the applied impedance calibration code when the calibration code update flag is not received within a specified time after transmitting the new impedance calibration code to the calibration control circuit.

3 . The memory device of claim 1 , wherein the calibration control circuit does not generate the calibration code update flag when the new impedance calibration code is outside the calibration code range.

4 . The memory device of claim 1 , wherein the calibration control circuit comprises:

a code range register configured to store the calibration code range; and

a code comparator configured to determine whether the new impedance calibration code is included in the calibration code range and generate the calibration code update flag when the new impedance calibration code is included in the calibration code range.

5 . The memory device of claim 4 , wherein the code comparator is configured to generate an abnormal code detection flag when the new impedance calibration code is not included in the calibration code range and store the abnormal code detection flag in a mode register.

6 . The memory device of claim 5 , further comprising:

control logic configured to transmit the abnormal code detection flag to a memory controller when receiving a mode register read command from the memory controller.

7 . The memory device of claim 5 , further comprising:

a temperature sensor configured to generate a temperature code corresponding to a temperature of the memory device,

wherein the code comparator comprises:

a first sub-comparator configured to determine whether the new impedance calibration code is included in a first calibration code range; and

a second sub-comparator configured to determine whether the new impedance calibration code is included in a second calibration code range, which is smaller than the first calibration code range, corresponding to the temperature code.

8 . The memory device of claim 7 , wherein the first sub-comparator is configured to:

receive the new impedance calibration code from the impedance calibration circuit;

transmit the new impedance calibration code to the second sub-comparator when the new impedance calibration code is included in the first calibration code range; and

output the abnormal code detection flag when the new impedance calibration code is outside the range of the first calibration code.

9 . The memory device of claim 8 , wherein the second sub-comparator is configured to:

receive the new impedance calibration code from the first sub-comparator;

output the calibration code update flag when the new impedance calibration code is included in the second calibration code range; and

output the abnormal code detection flag when the new impedance calibration code is outside the range of the second calibration code.

10 . The memory device of claim 7 , wherein the first calibration code range is determined based on a minimum calibration code and a maximum calibration code among test impedance calibration codes generated within an operating temperature range of the memory device.

11 . The memory device of claim 7 , wherein the second calibration code range is a range specified around each test impedance calibration code corresponding to each temperature code within an operating temperature range of the memory device.

12 . The memory device of claim 11 , wherein the second calibration code range is set the same in a plurality of temperature codes.

13 . The memory device of claim 11 , wherein the second calibration code range is set differently for each of a plurality of temperature codes.

14 . A memory device comprising:

a memory cell array;

an input/output circuit configured to control inputting of data to the memory cell array and outputting of data stored in the memory cell array;

an impedance calibration circuit configured to generate an impedance calibration code based on an external resistor for application to the input/output circuit as an applied impedance calibration code; and

a calibration control circuit configured to compare a new impedance calibration code received from the impedance calibration circuit with a calibration code range to generate a calibration code update flag when the new impedance calibration code is included in the calibration code range,

wherein the impedance calibration circuit comprises:

an impedance pad connected to the external resistor;

a pull-down driver connected to the impedance pad;

a code generator configured to compare a voltage of the impedance pad and a target voltage to generate a new impedance calibration code; and

a pull-down code control circuit configured to receive the new impedance calibration code and update the applied impedance calibration code to the new impedance calibration code when receiving the calibration code update flag within a specified time after transmitting the new impedance calibration code to the calibration control circuit.