Fully scannable memory arrays

1 . An array of memory cells, comprising a scan chain that shifts scan bits in adjacent memory cells in the scan chain using non-overlapping scan word line pulses to clock successive memory cells in the scan chain, wherein a shift direction of the scan chain is along a column of memory cells.

2 . The array of memory cells of claim 1 , wherein:

the memory cell includes a single latch.

3 . The array of memory cells of claim 1 , wherein the shift direction of the scan chain is from a scan chain input to a scan chain output, and wherein an update order of the adjacent cells in the scan chain is from a last cell in the scan chain to a first cell in the scan chain.

4 . The array of memory cells of claim 3 , further comprising:

a pulse generator to derive a pulse generator output from a clock pulse; and

a digital delay line with multiple outputs, configured to shift the pulse generator output along the multiple outputs to generate the non-overlapping scan word line pulses, wherein:

the multiple outputs are coupled with clock inputs of the memory cells.

5 . The array of memory cells of claim 4 , further comprising:

an input buffer including a series of input buffer cells that are aligned in a first dimension perpendicular to the shift direction of the scan chain; and

an address decoder to decode an address of a series of memory cells that are aligned in the first dimension;

wherein:

a scan shift action of an input buffer cell is triggered by the clock;

a shift action of a memory cell included in the series of memory cells is triggered by a scan word line pulse; and

the address decoder has outputs respectively coupled with clock inputs of memory cells included in the series of memory cells.

6 . The array of memory cells of claim 5 wherein:

the address decoder is a row address decoder;

the series of memory cells that are aligned in the first direction is a row of memory cells;

the series of input buffer cells that are aligned in a first direction is a row of input buffer cells; and

the shift direction of the scan chain is along a column of memory cells.

7 . The array of memory cells of claim 6 , wherein:

the scan chain input is included in a first buffer cell in a first column;

the scan chain continues from the first buffer cell in the first column via a first memory cell in the first column to a last memory cell in the first column;

the scan chain continues from the last memory cell in the first column to a first buffer cell in a second column;

the scan chain continues from the first buffer cell in the second column via a first memory cell in the second column to a last memory cell in the second column; and

the scan chain output is included in a last buffer cell in a last column.

8 . The array of memory cells of claim 5 , further comprising:

an additional buffer including a series of additional buffer cells that are aligned in the first direction, wherein the additional buffer separates a first part of the array of memory cells from a second part of the array of memory cells, and wherein an additional buffer cell includes a latch.

9 . A method of scanning an array of memory cells arranged in N rows and C columns, the array comprising a scan chain, the method comprising:

shifting scan bits in adjacent memory cells in the scan chain using non-overlapping scan word line pulses to clock successive memory cells in the scan chain, wherein a shift direction of the scan chain is along a column of memory cells.

10 . The method of claim 9 , wherein:

the shift direction of the scan chain is from a scan chain input to a scan chain output, and wherein the adjacent memory cells receive the non-overlapping scan word line pulses in a direction reverse from the shift direction of the scan chain.

11 . The method of claim 9 , further comprising:

copying a scan input value into an input buffer of a first column;

for each column c, copying a value from a memory cell (N−1, c) into an input buffer cell of column c+1, wherein c ranges from 0 to C−2;

providing a value of memory cell (N−1, C−1) to the scan chain output;

for each column c and each row r, copying a value from cell (r−1, c) into cell (r, c), wherein c ranges from 0 to C−1, and r ranges backward from N−1 to 1; and

for each column c, copying a value from an input buffer cell of column c into memory cell (0, c), wherein c ranges from 0 to C−1.

12 . An array of memory cells arranged in N rows, numbered 0 through N−1, and C columns, numbered 0 through C−1, each row comprising a word line multiplexer, and each column comprising a first scan multiplexer, a second scan multiplexer, a read multiplexer, and a column buffer cell, wherein:

each word line multiplexer, each first scan multiplexer, and each second scan multiplexer has a first input, a second input, and a scan enable input, and is configured to couple the first input with an output when the scan enable input is de-asserted and to couple the second input with the output when the scan enable input is asserted;

the second input of the first scan multiplexer in column 0 is coupled with a scan chain input;

in each column:

the output of the first scan multiplexer is coupled with an input of the column buffer cell;

an output of the column buffer cell is coupled with an input of the memory cell in row 0 and with the first input of the second scan multiplexer;

the output of the second scan multiplexer is coupled with inputs of the memory cells in rows 1 through N−1;

outputs of memory cells in rows 0 through N−1 are coupled with inputs of the read multiplexer; and

an output of the read multiplexer is coupled with the second input of the second scan multiplexer;

in each column c wherein c ranges from 0 through N−2, the output of the memory cell (N−1, c) is coupled with the second input of the first scan multiplexer in column c+1;

the output of memory cell (N−1, C−1) is coupled with a scan chain output; and

in each row:

the output of the word line multiplexer is coupled with CLK inputs of memory cells in columns 0 through C−1.

13 . A method of scanning an array of memory cells, wherein the array comprises a scan chain including at least two columns, coupled in series, and wherein each column comprises M of the memory cells, numbered 0 through M−1, each with a memory cell enable input, a first scan multiplexer, a second scan multiplexer, a read multiplexer, and a column buffer cell, and the array comprises M cell multiplexers, each with an output coupled with one of the M memory cell enable inputs of the M memory cells of the at least two columns, the method comprising:

copying a scan chain input value to a second input of the first scan multiplexer in a first column;

asserting clock inputs of the column buffer cells;

for each column:

copying an output value of the first scan multiplexer to an input of the column buffer cell;

copying an output value of the column buffer cell to an input of memory cell 0 and to a first input of the second scan multiplexer;

copying an output value of the read multiplexer to a second input of the second scan multiplexer;

copying an output value of the second scan multiplexer to inputs of memory cells m, wherein m ranges from 1 to M−1;

copying output values of memory cells m to inputs of the read multiplexer, wherein m ranges from 0 to M−1; and

for the first column copying an output value of memory cell M−1 to a second input of the first scan multiplexer in a second column;

for a last column, copying an output value of memory cell M−1 to a scan chain output value;

using a scan enable signal to select second inputs of the first scan multiplexer, the second scan multiplexer, and m cell multiplexers, wherein m ranges from 0 to M−1;

for each cell multiplexer m, wherein m ranges backward from M−1 to 0, applying a pulse to a second input of the cell multiplexer to enable memory cells m to copy a memory cell input value to a memory cell output; and

de-asserting the clock of the column buffer cells to enable the column buffers cells to copy their input values to their output.