Constant charge control for DC-DC converters
Disclosed herein is a DC-DC converter, including a high-side power switch coupled between an input voltage and a switched node and a low-side power switch coupled between the switched node and ground. An inductor is coupled between the switched node and an output node. An output capacitor is coupled between the output node and ground. A control circuit is configured to operate the high-side power switch in a constant charge mode of operation to vary on-time of the high-side power switch to maintain a constant amount of charge being transferred to the output capacitor during each charging cycle, independent of variation of the input voltage.
1 . A DC-DC converter, comprising:
a high-side power switch coupled between an input voltage and a switched node;
a low-side power switch coupled between the switched node and ground;
an inductor coupled between the switched node and an output node;
an output capacitor coupled between the output node and ground; and
a control circuit configured to operate the high-side power switch in a constant charge mode of operation to vary on-time of the high-side power switch to maintain a constant amount of charge being transferred to the output capacitor during each charging cycle, independent of variation of the input voltage.
2 . The DC-DC converter of claim 1 , wherein the control circuit comprises:
a peak inductor current threshold generator configured to generate a threshold voltage indicative of a desired peak current through the inductor based upon the input voltage and an output voltage at the output node;
a peak current control circuit configured to compare the threshold voltage to a ramp voltage indicative of a current through the inductor; and
a controller configured to turn off the low-side power switch while turning on the high-side power switch until the ramp voltage becomes equal to the threshold voltage, and then turning off the high-side power switch while turning on the low-side power switch.
3 . The DC-DC converter of claim 2 , wherein the peak current control circuit comprises:
a comparator configured to compare the ramp voltage indicative of the current through the inductor to the threshold voltage, and generate a control signal based thereupon;
a current subtractor configured to generate an output including ramp current by subtracting a current indicative of the output voltage from a current indicative of the input voltage;
a peak current capacitor; and
a switch configured to couple the peak current capacitor to ground when the control signal is asserted, and to couple the peak current capacitor to receive the ramp current when the control signal is deasserted.
4 . The DC-DC converter of claim 3 , wherein the peak inductor current threshold generator comprises:
a current divisor configured to generate a division current based upon a division operation performed on the current indicative of the input voltage and the output of the current subtractor; and
a rooting circuit configured to perform a square rooting operation on the division current and produce an output thereof as the threshold voltage.
5 . The DC-DC converter of claim 4 , further comprising a current mirror configured to mirror the division current generated by the current divisor to the rooting circuit.
6 . The DC-DC converter of claim 4 , wherein the rooting circuit comprises:
a first transistor coupled between a supply voltage and a first node, the first transistor having a gate coupled to be controlled as a function of the division current;
a second transistor coupled between the first node and ground, the second transistor having a gate coupled to be controlled as a function of a voltage at a second node; and
a third transistor coupled between the second node and ground, the third transistor having a gate coupled to be controlled as a function of the voltage at the second node.
7 . The DC-DC converter of claim 6 , wherein the rooting circuit further comprises a fourth transistor coupled between the supply voltage and the second node, the fourth transistor being controlled as a function of a voltage at a third node.
8 . The DC-DC converter of claim 7 , wherein the rooting circuit further comprises a fifth transistor diode coupled between a fourth node and ground, with the division current being sourced to the fourth node.
9 . The DC-DC converter of claim 8 , wherein:
the first transistor comprises a first n-channel transistor having a drain connected to the supply voltage, a source connected to the first node, and a gate connected to the fourth node;
the second transistor comprises a second n-channel transistor having a drain connected to the first node, a source connected to ground, and a gate connected to the second node;
the third transistor comprises a third n-channel transistor having a drain connected to the second node, a source connected to ground, and a gate connected to the second node;
the fourth transistor comprises a first p-channel transistor having a source connected to the supply voltage, a drain connected to the second node, and a gate connected to the third node; and
the fifth transistor comprises a fourth n-channel transistor having a drain connected to the fourth node, a source connected to ground, and a gate connected to the fourth node.
10 . The DC-DC converter of claim 9 ,
further comprising a current mirror configured to mirror the division current generated by the current divisor to the rooting circuit; and
wherein the current mirror comprises:
a sixth transistor coupled to receive the division current;
a seventh transistor coupled in a mirroring relationship with the sixth transistor to thereby sink a replica of the division current from the third node;
an eighth transistor coupled to have replica of the division current sunk therefrom;
a ninth transistor coupled in a mirroring relationship with the eighth transistor to thereby source the division current to the fourth node; and
a tenth transistor coupled in a mirroring relationship with the ninth transistor.
11 . The DC-DC converter of claim 10 , wherein:
the sixth transistor comprises a fifth n-channel transistor having a drain coupled to receive the division current, a gate connected to its drain, and a source connected to ground;
the seventh transistor comprises a sixth n-channel transistor having a drain connected to the third node, a source connected to ground, and a gate connected to the third node, the seventh transistor being in a mirror relationship with the sixth transistor;
the eighth transistor comprises a second p-channel transistor having a source connected to the supply voltage, a drain connected to the third node, and a gate connected to the third node;
the ninth transistor comprises a third p-channel transistor having a source connected to the supply voltage, a drain connected to the fourth node, and a gate connected to the third node; and
the tenth transistor comprises a fourth p-channel transistor (MP 3 ) having a source connected to the supply voltage, a drain connected to ground, and a gate connected to the third node.
12 . A method of operating a DC-DC converter, comprising:
turning off a low-side power switch and turning on a high-side power switch in response to each time a feedback voltage is equal lower than a reference voltage to thereby begin a charging cycle; and
setting on-time of the high-side power switch to maintain a constant amount of charge being transferred from an input node, in cooperation with an inductor, to an output capacitor during each charging cycle, independent of variation of an input voltage at the input node.
13 . The method of claim 12 , wherein setting the on-time of the high-side power switch to maintain the constant amount of charge being transferred from the input node, in cooperation with the inductor, to the output capacitor during each charging cycle, independent of the input voltage at the input node is performed by:
generating a threshold voltage indicative of a desired peak current through the inductor based upon the input voltage and an output voltage at an output node;
comparing the threshold voltage to a ramp voltage indicative of a current through the inductor; and
turning off the low-side power switch while turning on the high-side power switch until the ramp voltage becomes equal to the threshold voltage, then turning off the high-side power switch while turning on the low-side power switch, then turning off the low-side power switch when the current through the inductor zero crosses.
14 . The method of claim 13 , wherein generating the threshold voltage comprises:
generating a division current based upon a division operation performed on a current indicative of the input voltage and an output of a difference between the current indicative of the input voltage and a current indicative of the output voltage; and
performing a square rooting operation on the division current and producing an output thereof as the threshold voltage.
15 . The method of claim 14 , further comprising mirroring the division current generated by the current divisor to the rooting circuit using a current mirror.