IP Library › Granted Patent US 12700800

Granted Patent B2

US 12700800 · App. 18/498,163 · Granted Aug 4, 2026

Multi-function high side field-effect transistor driver circuit

Inventors: Bradford Hunter (Austin, TX); Jing Ye (Dallas, TX); Xiaoqiu Summer Huang (Dallas, TX); Terry Sculley (Lewisville, TX)

Assignee: TEXAS INSTRUMENTS INCORPORATED

H02M3/07 H02M1/0006 H02M1/088 H02M1/32

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Quick Facts

Patent No.: US 12700800
App. No.: 18/498,163
Granted: Aug 4, 2026
Kind: B2

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Abstract

An integrated circuit comprises a charge pump connected to a power source terminal and to a ground terminal, the charge pump having a charge pump output terminal; and a switch matrix having a plurality of switch matrix inputs and a plurality of switch matrix outputs, wherein pairs of the plurality of switch matrix outputs are connected to respective ones of a respective plurality of output terminals, and wherein the charge pump output terminal is connected to a first subset comprising at least three of the plurality of switch matrix inputs.

Claims (59)

1 . An integrated circuit comprising:

a circuit having an input and an output, the circuit configurable to receive a first voltage at the input and provide a second voltage higher than the first voltage;

a first switch circuit having inputs coupled to the input and the output of the circuit, a first switch control input, and a first switch output, the first switch circuit configurable to connect one of the input or the output of the circuit to the first switch output responsive to states of the first switch control input; and

a second switch circuit having inputs coupled to the output of the circuit and a power terminal, a second switch control input, and a second switch output, the second switch circuit configurable to connect one of the output of the circuit or the power terminal to the second switch output responsive to states of the second switch control input.

2 . The integrated circuit of claim 1 , wherein:

the first switch circuit includes a first semiconductor switch and a second semiconductor switch, the first semiconductor switch coupled between the input of the circuit and the first switch output, and the second semiconductor switch coupled between the output of the circuit and the first switch output;

the second switch circuit includes a third semiconductor switch and a fourth semiconductor switch, the third semiconductor switch coupled between the output of the circuit and the second switch output, and the fourth semiconductor switch coupled between the power terminal and the second switch output;

the input of the circuit is coupled to a power source terminal; and

the integrated circuit further comprises a third switch circuit having inputs coupled to the output of the circuit and the power terminal, a third switch control input, and a third switch output, the third switch circuit including a fifth semiconductor switch coupled between the output of the circuit and the third switch output and a sixth semiconductor switch coupled between the power terminal and the third switch output.

3 . The integrated circuit of claim 2 , wherein the power terminal is coupled to a power supply terminal.

4 . The integrated circuit of claim 2 , further comprising:

a seventh semiconductor switch coupled between a fourth switch output and the output of the circuit; and

an eighth semiconductor switch coupled between the fourth switch output and the input of the circuit.

5 . The integrated circuit of claim 2 , wherein the first semiconductor switch comprises:

an input transistor having a first input transistor terminal, a second input transistor terminal, and an input transistor control terminal;

an output transistor having a first output transistor terminal, a second output transistor terminal, and an output transistor control terminal; and

a control transistor having a first control transistor terminal, a second control transistor terminal, and a control transistor control terminal.

6 . The integrated circuit of claim 5 , wherein the first semiconductor switch further comprises:

a first current-limiting element having a first current-limiting element terminal and a second current-limiting element terminal, wherein the first current-limiting element terminal is coupled to the second input transistor terminal and to the first output transistor terminal, and wherein the second current-limiting element terminal is coupled to the first control transistor terminal;

a first voltage clamp circuit having a first voltage clamp circuit terminal and a second voltage clamp circuit terminal, wherein the first voltage clamp circuit terminal is coupled to the first control transistor terminal, and wherein the second voltage clamp circuit terminal is coupled to the second input transistor terminal and to the first output transistor terminal; and

a second current-limiting element having a third current-limiting element terminal and a fourth current-limiting element terminal, wherein the third current-limiting element terminal is coupled to the second control transistor terminal.

7 . The integrated circuit of claim 6 , wherein the first semiconductor switch further comprises:

a third current-limiting element having a fifth current-limiting element terminal and a sixth current-limiting element terminal, wherein the fifth current-limiting element terminal is coupled to the first input transistor terminal, and wherein the second current-limiting element terminal is coupled to the output transistor control terminal; and

a second voltage clamp circuit having a third voltage clamp circuit terminal and a fourth voltage clamp circuit terminal, wherein the third voltage clamp circuit terminal is coupled to the second input transistor terminal and to the first output transistor terminal, and wherein the fourth voltage clamp circuit terminal is coupled to the output transistor control terminal.

8 . The integrated circuit of claim 1 , wherein the circuit is configurable to provide the second voltage by adding an offset to the first voltage.

9 . The integrated circuit of claim 8 , wherein the circuit is, includes, or is part of a charge pump circuit.

10 . The circuit of claim 1 , wherein the power terminal is a first power terminal, and the circuit further comprises:

a first transistor and a second transistor coupled between a second power terminal and the first power terminal, the first transistor and second transistors configurable to enable or disable a first current path between the first and second power terminals; and

a third transistor and a fourth transistor coupled between a second power terminal and the first power terminal, the third and fourth transistors configurable to enable or disable a second current path between the first and second power terminals,

wherein each of the first and third transistors has a respective control terminal coupled to the first switch output, and each of the second and fourth transistors has a respective control terminal coupled to the second switch output.

11 . The circuit of claim 10 , wherein each of the first, second, third, and fourth transistors includes a respective n-channel transistor.

12 . A circuit comprising:

a first power terminal;

a second power terminal;

a ground terminal;

a first output terminal;

a second output terminal;

a circuit having an input and an output, the input of the circuit coupled to the first power terminal, the circuit configurable to receive a first voltage at the input and provide a second voltage higher than the first voltage;

a first switch circuit having inputs coupled to the input and the output of the circuit, a first switch control input, and a first switch output coupled to the first output terminal, the first switch circuit configurable to connect one of the input or the output of the circuit to the first switch output responsive to states of the first switch control input; and

a second switch circuit having inputs coupled to the output of the circuit and the second power terminal, a second switch control input, and a second switch output coupled to the second output terminal, the second switch circuit configurable to connect one of the output of the circuit or the second power terminal to the second switch output responsive to states of the second switch control input.

13 . The circuit of claim 12 , wherein the first power terminal is coupled to a power source terminal, and the second power terminal is coupled to a power supply terminal.

14 . The circuit of claim 12 , wherein the first switch circuit includes a semiconductor switch, the semiconductor switch including:

an input transistor having a first input transistor terminal, a second input transistor terminal, and an input transistor control terminal;

an output transistor having a first output transistor terminal, a second output transistor terminal, and an output transistor control terminal; and

a control transistor having a first control transistor terminal, a second control transistor terminal, and a control transistor control terminal.

15 . The circuit of claim 14 , wherein the semiconductor switch includes:

a first current-limiting element having a first current-limiting element terminal and a second current-limiting element terminal, the first current-limiting element terminal is coupled to the second input transistor terminal and to the first output transistor terminal, and the second current-limiting element terminal is coupled to the first control transistor terminal;

a first voltage clamp circuit having a first voltage clamp circuit terminal and a second voltage clamp circuit terminal, the first voltage clamp circuit terminal is coupled to the first control transistor terminal, and the second voltage clamp circuit terminal is coupled to the second input transistor terminal and to the first output transistor terminal; and

a second current-limiting element having a third current-limiting element terminal and a fourth current-limiting element terminal, the third current-limiting element terminal is coupled to the second control transistor terminal.

16 . The circuit of claim 15 , wherein the semiconductor switch further comprises:

a second voltage clamp circuit having a third voltage clamp circuit terminal and a fourth voltage clamp circuit terminal, the third voltage clamp circuit terminal is coupled to the second input transistor terminal and to the first output transistor terminal, and the fourth voltage clamp circuit terminal is coupled to the output transistor control terminal.

17 . The circuit of claim 12 , wherein the circuit is configurable to provide the second voltage by adding an offset to the first voltage.

18 . The circuit of claim 17 , wherein the circuit is, includes, or is part of a charge pump circuit.

19 . The circuit of claim 12 , further comprising:

20 . The circuit of claim 19 , wherein each of the first, second, third, and fourth transistors includes a respective n-channel transistor.