IP Library › Granted Patent US 12700840
Granted Patent B2
US 12700840 · App. 18/175,785 · Granted Aug 4, 2026

Low second harmonic single ended class AB amplifier

Inventors: Ravikumar Pattipaka (Bangalore, IN); Raja Sekhar (Bangalore, IN); Sandeep Kesrimal Oswal (Bangalore, IN)
Assignee: TEXAS INSTRUMENTS INCORPORATED
H03F3/45076H03F1/26H03F3/211
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Quick Facts
Patent No.
US 12700840
App. No.
18/175,785
Granted
Aug 4, 2026
Kind
B2
Abstract

In an example, a circuit includes a high side output transistor having a control terminal coupled to a first capacitor, and includes a low side output transistor having a control terminal coupled to a second capacitor and a balancing capacitor. The circuit includes a first differential input stage configured to receive a differential input and provide a first output current to the control terminal of the high side output transistor. The circuit includes a second differential input stage configured to receive the differential input and provide a second output current to the control terminal of the low side output transistor. The circuit includes a floating battery coupled to the control terminal of the high side output transistor and the control terminal of the low side output transistor. The balancing capacitor balances a gate-to-source capacitance of the low side output transistor with a gate-to-source capacitance of the high side output transistor.

Claims (50)

1 . A circuit, comprising:

a first differential input stage including:

a first positive input terminal coupled to a control terminal of a first transistor, and

a first negative input terminal coupled to a control terminal of a second transistor;

a second differential input stage including:

a second positive input terminal coupled to a control terminal of a third transistor;

a second negative input terminal coupled to a control terminal of a fourth transistor; and

a balancing capacitor;

a floating battery including a fifth transistor and a sixth transistor, the floating battery coupled to the second transistor and the fourth transistor;

an output stage including:

a high side output transistor having a control terminal coupled to the first differential input stage and the floating battery;

a low side output transistor having a control terminal coupled to the second differential input stage, the floating battery, and the balancing capacitor;

a first compensation capacitor coupled to the floating battery; and

a second compensation capacitor coupled to the floating battery.

2 . The circuit of claim 1 , wherein the first differential input stage includes a current mirror coupled to a drain of the first transistor and a drain of the second transistor, and wherein the drain of the second transistor is coupled to the control terminal of the high side output transistor.

3 . The circuit of claim 1 , wherein the first compensation capacitor has a first terminal coupled to the control terminal of the high side output transistor and a second terminal coupled to a drain of the high side output transistor.

4 . The circuit of claim 1 , wherein the second compensation capacitor has a first terminal coupled to the control terminal of the low side output transistor and a second terminal coupled to a drain of the low side output transistor.

5 . The circuit of claim 1 , wherein the balancing capacitor has a first terminal coupled to the control terminal of the low side output transistor and a second terminal coupled to a source of the low side output transistor.

6 . The circuit of claim 1 , wherein the high side output transistor and the low side output transistor are configured as a class AB output stage.

7 . The circuit of claim 1 , wherein the output stage includes a current source coupled to a voltage source and to the control terminal of the high side output transistor.

8 . The circuit of claim 1 , wherein the first differential input stage includes a current source coupled to a source of the first transistor and a source of the second transistor.

9 . The circuit of claim 1 , wherein the fifth transistor has a source coupled to a drain of the sixth transistor, and the fifth transistor has a drain coupled to a source of the sixth transistor.

10 . A circuit, comprising:

a high side output transistor having a control terminal coupled to a first capacitor;

a low side output transistor having a control terminal coupled to a second capacitor and to a balancing capacitor;

a first differential input stage configured to receive a differential input and provide a first output current to the control terminal of the high side output transistor;

a second differential input stage configured to receive the differential input and provide a second output current to the control terminal of the low side output transistor;

a floating battery coupled to the control terminal of the high side output transistor and the control terminal of the low side output transistor; and

wherein the balancing capacitor is configured to balance a gate-to-source capacitance of the low side output transistor with a gate-to-source capacitance of the high side output transistor.

11 . The circuit of claim 10 , wherein the floating battery is configured to bias the high side output transistor and the low side output transistor.

12 . The circuit of claim 10 , wherein a current through the floating battery is the same for a positive half cycle of an output voltage and a negative half cycle of the output voltage.

13 . The circuit of claim 10 , wherein the first differential input stage includes a first positive input terminal coupled to a control terminal of a first transistor, and a first negative input terminal coupled to a control terminal of a second transistor.

14 . The circuit of claim 10 , wherein the first output current equals the second output current.

15 . The circuit of claim 10 , wherein the first differential input stage includes a first transistor and a second transistor, a source of the first transistor coupled to a source of the second transistor, and a current mirror coupled to a drain of the first transistor and a drain of the second transistor.

16 . The circuit of claim 10 , wherein the floating battery includes a first transistor and a second transistor, wherein the first transistor has a source coupled to a drain of the second transistor, and the first transistor has a drain coupled to a source of the second transistor.

17 . The circuit of claim 10 , wherein the high side output transistor and the low side output transistor are configured as a class AB output stage.

18 . The circuit of claim 10 , further comprising a current source coupled to the control terminal of the high side output transistor and to a voltage source.

19 . A system, comprising:

a transducer;

a transconductance amplifier having an input coupled to an output of the transducer;

an operational amplifier having an input coupled to an output of the transconductance amplifier, the operational amplifier including:

a first differential input stage;

a second differential input stage having a balancing capacitor;

a floating battery coupled to the first differential input stage and the second differential input stage;

an output stage including:

a high side output transistor having a control terminal coupled to the first differential input stage and the floating battery;

a low side output transistor having a control terminal coupled to the second differential input stage and the floating battery;

a first compensation capacitor coupled to the floating battery; and

a second compensation capacitor coupled to the floating battery.

20 . The system of claim 19 , wherein the balancing capacitor is configured to balance a gate-to-source capacitance of the low side output transistor with a gate-to-source capacitance of the high side output transistor.