System and method for reducing circuit elements in high-performance flip-flops
View Patent ↗A latch circuit comprising a tristate driver and a storage feedback loop and having minimal circuit elements is disclosed. The tristate driver and feedback loop couple to internal nodes of a separate latch circuit to reduce total circuit element count by collapsing elements with common functionality into a single circuit element. The latch circuit presents only one transistor gate load to a clock signal, and the output of the separate latch is coupled to the input of the latch circuit to form a flip-flop. The flip-flop generates an output signal based on a received input signal when the clock signal is at second level and stores the received input signal when the clock signal is at first level. The flip-flop is fully static, contention-free, with near-zero setup time, with less circuit elements than prior arts, and can be configured to integrate multi-input logic functions.
1 . A flip-flop circuit comprising:
an input terminal for receiving a main input signal;
a clock terminal for receiving a clock signal;
an output terminal for sending an output signal; and
an input propagation unit comprising:
a first clock-activated transistor as the first top-most transistor of a first stack structure;
a second clock-activated transistor as the second top-most transistor of a second stack structure;
a first top node;
a second top node;
a first bottom node;
a second bottom node;
a first keeper device;
a second keeper device;
a latch, wherein said latch having at most one clock-activated transistor and wherein said latch couples to either said first top node and said second top node, or said first bottom node and said second bottom node and wherein said latch is coupled to said first keeper device of said input propagation unit;
wherein said first keeper device is activated upon the discharging of said first top node to low power supply, wherein said second keeper device is activated upon the discharging of said second top node to said low power supply;
wherein said latch further comprises:
a tristate driver to receive a first input from an output of the input propagation unit and a second input from said clock signal;
a keeper sub-circuit to maintain said storage node at constant level when said clock signal is at first level; and
an output buffer to isolate output signal from said storage node;
wherein said tristate driver writes said first input to a storage node when said clock signal is at second level;
wherein said tristate driver comprises a third clock-activated transistor configured as a pull-down network coupled to either said first bottom node or said second bottom node.
2 . The flip-flop circuit of claim 1 , wherein said third clock-activated transistor activates said first keeper device when said main input signal is at second level and said clock signal is at second level, thereby providing said first top node of the input propagation unit with an alternative low-impedance path to low power supply.
3 . A flip-flop circuit comprising:
an input terminal for receiving a main input signal;
a clock terminal for receiving a clock signal;
an output terminal for sending an output signal; and
an input propagation unit comprising:
a first clock-activated transistor as the first top-most transistor of a first stack structure;
a second clock-activated transistor as the second top-most transistor of a second stack structure;
a first top node;
a second top node;
a first bottom node;
a second bottom node;
a first keeper device;
a second keeper device;
a latch, wherein said latch having at most one clock-activated transistor and wherein said latch couples to either said first top node and said second top node, or said first bottom node and said second bottom node and wherein said latch is coupled to said first keeper device of said input propagation unit;
wherein said first keeper device is activated upon the discharging of said first top node to low power supply, wherein said second keeper device is activated upon the discharging of said second top node to said low power supply;
wherein said latch further comprises:
a tristate driver to receive a first input from an output of the input propagation unit and a second input from said clock signal;
a keeper sub-circuit to maintain said storage node at constant level when said clock signal is at first level; and
an output buffer to isolate output signal from said storage node;
wherein said tristate driver writes said first input to a storage node when said clock signal is at second level;
wherein the keeper sub-circuit comprises a pull-up transistor coupled to either said first top node or second top node and wherein said keeper sub-circuit further comprises a pull-down transistor coupled to either said first bottom node or said second bottom node.
4 . The flip-flop circuit of claim 3 , wherein said pull-up transistor enables said storage node with a low impedance path to high power supply via said first top node or said second top node when said clock signal is at first level.
5 . The flip-flop circuit of claim 3 , wherein said first top node is coupled to the first top-most transistor and said second top node is coupled to the second top-most transistor.
6 . The flip-flop circuit of claim 3 , wherein the activation of said first keeper device and said second keeper device is independent of changes in said main input signal when said clock signal is at second level.
7 . The flip-flop circuit of claim 3 , wherein said first clock-activated transistor and said second clock-activated transistor reduce the number of intermediate nodes within said first stack structure and said second stack structure from toggling when said main input signal is constant, eliminate contention at said first top node and said second top node when said clock signal transitions to first level, and reduce charge sharing between said first top node and said second top node and intermediate nodes of the first and second stack structures when the clock signal is at first level.
8 . A flip-flop circuit comprising:
an input terminal for receiving a main input signal;
a clock terminal for receiving a clock signal;
an output terminal for sending an output signal; and
an input propagation unit comprising:
a first clock-activated transistor as the first top-most transistor of a first stack structure;
a second clock-activated transistor as the second top-most transistor of a second stack structure;
a first top node;
a second top node;
a first bottom node;
a second bottom node;
a first keeper device;
a second keeper device;
a latch, wherein said latch having at most one clock-activated transistor and wherein said latch couples to either said first top node and said second top node, or said first bottom node and said second bottom node and wherein said latch is coupled to said first keeper device of said input propagation unit;
wherein said first keeper device is activated upon the discharging of said first top node to low power supply, wherein said second keeper device is activated upon the discharging of said second top node to said low power supply;
wherein said latch further comprises:
a tristate driver to receive a first input from an output of the input propagation unit and a second input from said clock signal;
a keeper sub-circuit to maintain said storage node at constant level when said clock signal is at first level; and
an output buffer to isolate output signal from said storage node;
wherein said tristate driver writes said first input to a storage node when said clock signal is at second level;
wherein said output signal of said output buffer is either of same or opposite polarity to said main input signal.
9 . The flip-flop circuit of claim 8 , wherein said first top node and said second top node are charged to second level when said clock signal is at first level, and wherein said first bottom node and said second bottom node are discharged to first level when said clock signal is at first level.
10 . The flip-flop circuit of claim 8 , wherein said first top node is coupled to the first top-most transistor and said second top node is coupled to the second top-most transistor.
11 . The flip-flop circuit of claim 8 , wherein the activation of said first keeper device and said second keeper device is independent of changes in said main input signal when said clock signal is at second level.
12 . The flip-flop circuit of claim 8 , wherein said first keeper device is configured to enable said first top node with an alternative low-impedance path to said low power supply when said main input signal changes while said clock signal remains at second level, and said second keeper device is configured to maintain a primary low-impedance path to said low power supply for said second top node when said main input signal changes while said clock signal remains at second level.
13 . The flip-flop circuit of claim 8 , wherein said first clock-activated transistor and said second clock-activated transistor reduce the number of intermediate nodes within said first stack structure and said second stack structure from toggling when said main input signal is constant, eliminate contention at said first top node and said second top node when said clock signal transitions to first level, and reduce charge sharing between said first top node and said second top node and intermediate nodes of the first and second stack structures when the clock signal is at first level.
14 . The flip-flop circuit of claim 8 , wherein said first stack structure and said second stack structure are configured to receive multi-input logic.
15 . The flip-flop circuit of claim 8 , wherein said first data transistor is the first top-most transistor of the first stack structure and said second data transistor is the second top-most transistor of said second stack structure.
16 . The flip-flop circuit of claim 8 , wherein said latch comprises at most one clock-activated transistor and merges the pull-up functionality of the pull-up transistor from the keeper sub-circuit with either said first top node or said second top node.
17 . The flip-flop circuit of claim 8 , wherein the first top node shares a source terminal from the latch and are coupled to the shared bottom node of the input propagation unit.
18 . The flip-flop circuit of claim 8 , wherein said pull-up transistor enables said storage node with a low impedance path to high power supply via said first top node or said second top node when said clock signal is at first level.
19 . A flip-flop circuit comprising:
an input terminal for receiving a main input signal;
a clock terminal for receiving a clock signal;
an output terminal for sending an output signal; and
an input propagation unit comprising:
a first clock-activated transistor as the first top-most transistor of a first stack structure;
a second clock-activated transistor as the second top-most transistor of a second stack structure;
a first top node and a second top node;
a first bottom node and a second bottom node;
a first keeper device;
a second keeper device;
a latch, wherein said latch is coupled to either said first top node and said second top node, or said first bottom node and said second bottom node and wherein said latch is coupled to said first keeper device of said input propagation unit;
wherein said first keeper device is activated upon the discharging of said first top node to low power supply, wherein said second keeper device is activated upon the discharging of said second top node to said low power supply.
20 . The flip-flop circuit of claim 19 , wherein said first top node and said second top node are charged to second level when said clock signal is at first level, and wherein said first bottom node and said second bottom node are discharged to a first level when said clock signal is at a first level.