IP Library › Granted Patent US 12700853
Granted Patent B2
US 12700853 · App. 18/733,960 · Granted Aug 4, 2026

Set-tolerant comparator

Inventor: Aaron Chen (Plano, TX)
Assignee: TEXAS INSTRUMENTS INCORPORATED
H03K3/02337H03K3/02335
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Quick Facts
Patent No.
US 12700853
App. No.
18/733,960
Granted
Aug 4, 2026
Kind
B2
Abstract

A comparator includes a differential input, an output, a pair of first transistors coupled to the differential input, a pair of second transistors coupled to the output, and a SET protection circuit. Gate terminals of the pair of first transistors are coupled to the differential input of the comparator. The second terminals of the pair of second transistors are coupled to the second terminals of the pair of first transistors. The SET protection circuit has a current source and a transistor. The transistor of the SET protection circuit has a first terminal coupled to the body terminals of the pair of first transistors to bias the body terminals of the pair of first transistors separate from the first terminals of the pair of first transistors. A gate terminal of the transistor of the SET protection circuit is coupled to a terminal of the differential input of the comparator.

Claims (43)

1 . A circuit, comprising:

a first input;

a second input;

an output;

a first transistor including a first terminal, a second terminal, a gate terminal and a body terminal, the gate terminal of the first transistor coupled to the first input of the circuit;

a second transistor including a first terminal, a second terminal, a gate terminal and a body terminal, the body terminal of the second transistor coupled to the body terminal of the first transistor, the first terminal of the first transistor coupled to the first terminal of the second transistor, and the gate terminal of the second transistor coupled to the second input of the circuit;

a third transistor including a first terminal, a second terminal, and a control terminal, the second terminal of the third transistor coupled to the second terminal of the first transistor;

a fourth transistor including a first terminal, a second terminal, and a control terminal, the second terminal of the fourth transistor coupled to the second terminal of the second transistor and coupled to the output of the circuit; and

a fifth transistor including a first terminal, a second terminal, a gate terminal and a body terminal, the gate terminal of the fifth transistor coupled to the gate terminal of the first transistor, the first terminal of the fifth transistor coupled to the body terminal of the fifth transistor, coupled to the body terminal of the first transistor and coupled to the body terminal of the second transistor.

2 . The circuit of claim 1 , further comprising:

a first supply rail; and

a second supply rail, the first terminal of the fifth transistor coupled to the first supply rail and the second terminal of the fifth transistor coupled to the second supply rail, the first terminal of the first transistor and the first terminal of the second transistor coupled to the second supply rail, and the second terminal of the third transistor and the second terminal of the fourth transistor coupled to the second supply rail.

3 . The circuit of claim 2 , further comprising:

a first current source coupled to the first supply rail and coupled to the first terminal of the fifth transistor; and

a second current source coupled to the first supply rail, coupled to the first terminal of the first transistor and the first terminal of the second transistor.

4 . The circuit of claim 3 :

the first current source configured to bias the first terminal of the fifth transistor, the body terminal of the first transistor and the body terminal of the second transistor; and

the second current source configured to bias the first terminal of the first transistor and the first terminal of the second transistor independently from the first terminal of the fifth transistor, the body terminal of the first transistor and the body terminal of the second transistor.

5 . The circuit of claim 1 , wherein the second terminal of the third transistor is coupled to the body terminal of the third transistor, coupled to the gate terminal of the third transistor and coupled to the gate terminal of the fourth transistor.

6 . The circuit of claim 1 , further comprising:

an RC circuit coupled to the output of the circuit and the second terminal of the second transistor.

7 . The circuit of claim 1 , further comprising:

a hysteresis circuit having an input and an output, the output of the hysteresis circuit coupled to the first input of the circuit; and

an electrostatic discharge (ESD) circuit having a first terminal, a second terminal, and a third terminal, the first terminal of the ESD circuit coupled to the first terminal of the first transistor and the first terminal of the second transistor, the second terminal of the ESD circuit coupled to the gate terminal of the second transistor, and the third terminal of the ESD circuit coupled to the first input of the circuit and coupled to the output of the hysteresis circuit.

8 . The circuit of claim 1 , wherein the first transistor comprises a first P-channel metal-oxide semiconductor (PMOS) transistor, the second transistor comprises a second PMOS transistor, the third transistor comprises a first N-channel metal-oxide semiconductor (NMOS) transistor, the fourth transistor comprises a second NMOS transistor, and the fifth transistor comprises a third PMOS transistor.

9 . The circuit of claim 1 , wherein the first transistor comprises a first N-channel metal-oxide semiconductor (NMOS) transistor, the second transistor comprises a second NMOS transistor, the third transistor comprises a first P-channel metal-oxide semiconductor (PMOS) transistor, the fourth transistor comprises a second PMOS transistor, and the fifth transistor comprises a third NMOS transistor.

10 . A circuit, comprising:

a differential input;

an output;

a first transistor including a first terminal, a second terminal, a gate terminal and a body terminal, the gate terminal of the first transistor coupled to the differential input of the circuit;

a second transistor including a first terminal, a second terminal, a gate terminal and a body terminal, the body terminal of the second transistor coupled to the body terminal of the first transistor, the first terminal of the first transistor coupled to the first terminal of the second transistor, and the gate terminal of the second transistor coupled to the differential input of the circuit;

a third transistor including a first terminal, a second terminal, and a gate terminal, the second terminal of the third transistor coupled to the second terminal of the first transistor;

a fourth transistor including a first terminal, a second terminal, and a gate terminal, the second terminal of the fourth transistor coupled to the second terminal of the second transistor and coupled to the output of the circuit; and

a protection circuit having a transistor, the transistor of the protection circuit having a first terminal, a second terminal, a gate terminal and a body terminal, the first terminal of the transistor of the protection circuit coupled to the body terminal of the transistor of the protection circuit, coupled to the body terminal of the first transistor and coupled to the body terminal of the second transistor, the protection circuit configured to bias the body terminal of the first transistor and the body terminal of the second transistor independently from the first terminal of the first transistor and the first terminal of the second transistor.

11 . The circuit of claim 10 , further comprising:

a first current source coupled to the first terminal of the transistor of the protection circuit; and

a second current source coupled to the first terminal of the first transistor and coupled to the first terminal of the second transistor.

12 . The circuit of claim 10 , further comprising:

a resistor having a first terminal and a second terminal, the first terminal of the resistor coupled to the second terminal of the transistor of the protection circuit, and the second terminal of the resistor coupled to the first terminal of the third transistor, coupled to the first terminal of the fourth transistor, and coupled to the gate terminal of the third transistor; and

a diode coupled to the gate terminal of the third transistor, coupled to the gate terminal of the fourth transistor, coupled to the first terminal of the third transistor and coupled to the first terminal of the fourth transistor.

13 . The circuit of claim 10 , further comprising:

a delay component having an input and an output, the input of the delay component coupled to the output of the circuit; and

a voltage regulator having an input and an output, the input of the voltage regulator coupled to the output of the delay component, and the output of the voltage regulator coupled to at least one terminal of the differential input of the circuit.