IP Library › Granted Patent US 12700855
Granted Patent B2
US 12700855 · App. 18/496,495 · Granted Aug 4, 2026

Enhancement of linearity for digitally controlled delay line

Inventors: Ahmed Safwat Mohamed Aboelenein Elmallah (San Jose, CA); Amr Tarek Ahmed Abdelrazik Khashaba (San Jose, CA); Mohammed Mohsen Abdulsalam Abdullatif (San Jose, CA); Tamer Mohammed Ali (San Jose, CA)
Assignee: MEDIATEK INC.
H03K5/14H03K5/135
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Quick Facts
Patent No.
US 12700855
App. No.
18/496,495
Granted
Aug 4, 2026
Kind
B2
Abstract

A digitally controlled delay device includes a plurality of first delay stages connected in series between a first input port and a first output port, and a plurality of second delay stages connected in series between a second input port and a second output port. Each first delay stage of the plurality of first delay stages includes a plurality of first delay elements and each second delay stage of the plurality of second delay stages includes a corresponding plurality of second delay elements. A controller performs complementary control based on a digital control signal by controlling one or more of the plurality of first delay elements to be in a first control state and controlling a corresponding one or more of the plurality of second delay elements to be in a second control state, opposite the first control state.

Claims (35)

1 . A digitally controlled delay device, the device comprising:

a plurality of first delay stages connected in series between a first input port and a first output port;

a plurality of second delay stages connected in series between a second input port and a second output port, wherein each first delay stage of the plurality of first delay stages includes a plurality of first delay elements and each second delay stage of the plurality of second delay stages includes a corresponding plurality of second delay elements; and

a controller configured to perform complementary control of the plurality of first delay elements in one of the plurality of first delay stages and the plurality of second delay elements in one of the plurality of second delay stages based on a digital control signal, wherein the digital control signal is not an input signal of each of the plurality of first delay stages and the plurality of second delay stages, the complementary control refers to controlling one or more of the plurality of first delay elements specified by the digital control signal to be in a first control state and controlling a corresponding one or more of the plurality of second delay elements to be in a second control state, opposite the first control state, and the first control state is an activation of the one or more of the plurality of first delay elements, and the second control state is a deactivation of the corresponding one or more of the plurality of second delay elements;

wherein the controller is further configured to perform complementary control for the plurality of first delay stages and the plurality of second delay stages such that, when the one or more of the plurality of first delay elements of the plurality of first delay stages are controlled to be in the first control state, corresponding one or more of the plurality of second delay elements of the plurality of second delay stages are controlled to be in the second control state.

2 . The device according to claim 1 , wherein the controller is further configured to maintain the first control state for the one or more of the plurality of first delay elements of the plurality of first delay stages when controlling additional ones of the plurality of the first delay elements of the plurality of first delay stages to be in the first control state.

3 . The device according to claim 1 , wherein the first control state is on and the second control state is off.

4 . The device according to claim 1 , wherein the plurality of first delay elements and the plurality of second delay elements are capacitors, inverters, or varactors.

5 . A digitally controlled delay device, the device comprising:

a plurality of first delay stages connected in series between a first input port and a first output port;

a plurality of second delay stages connected in series between a second input port and a second output port, wherein each first delay stage of the plurality of first delay stages includes a plurality of first delay elements and each second delay stage of the plurality of second delay stages includes a corresponding plurality of second delay elements; and

a controller configured to perform complementary control of the plurality of first delay elements in one of the plurality of first delay stages and the plurality of second delay elements in one of the plurality of second delay stages based on a digital control signal, wherein the digital control signal is not an input signal of each of the plurality of first delay stages and the plurality of second delay stages, the complementary control refers to controlling one or more of the plurality of first delay elements specified by the digital control signal to be in a first control state and controlling a corresponding one or more of the plurality of second delay elements to be in a second control state, opposite the first control state, and the first control state is an activation of the one or more of the plurality of first delay elements, and the second control state is a deactivation of the corresponding one or more of the plurality of second delay elements;

wherein the device is used in a phase locked loop (PLL).

6 . The device according to claim 5 , wherein the plurality of first delay stages are in a reference path of the PLL.

7 . The device according to claim 6 , wherein the plurality of second delay stages are in a feedback path of the PLL.

8 . A digitally controlled delay device comprising:

a plurality of first delay stages connected in series between a first input port and a first output port;

a plurality of second delay stages connected in series between a second input port and a second output port, wherein each first delay stage of the plurality of first delay stages includes a plurality of first delay elements and each second delay stage of the plurality of second delay stages includes a corresponding plurality of second delay elements; and

a controller configured to perform complementary control of the plurality of first delay elements in each of the plurality of first delay stages and the plurality of second delay elements in each of the plurality of second delay stages based on a digital control signal, wherein the digital control signal is not an input signal of each of the plurality of first delay stages and the plurality of second delay stages, the complementary control refers to controlling one or more of the plurality of first delay elements specified by the digital control signal to be in a first control state and controlling a corresponding one or more of the plurality of second delay elements to be in a second control state, opposite the first control state, and the first control state is an activation of the one or more of the plurality of first delay elements, and the second control state is a deactivation of the corresponding one or more of the plurality of second delay elements;

wherein the device is used in a phase locked loop (PLL).

9 . The device according to claim 8 , wherein the plurality of first delay stages are in a reference path of the PLL.

10 . The device according to claim 9 , wherein the plurality of second delay stages are in a feedback path of the PLL.

11 . The device according to claim 8 , wherein the first control state is on and the second control state is off.

12 . The device according to claim 8 , wherein the plurality of first delay elements and the plurality of second delay elements are capacitors, inverters, or varactors.

13 . A digitally controlled delay device comprising:

a plurality of first delay stages connected in series between a first input port and a first output port;

a plurality of second delay stages connected in series between a second input port and a second output port, wherein each first delay stage of the plurality of first delay stages includes a plurality of first delay elements and each second delay stage of the plurality of second delay stages includes a corresponding plurality of second delay elements; and

a controller configured to control, based on a code indicated by a digital control signal, the plurality of first delay elements in the plurality of first delay stages and the plurality of second delay elements in the plurality of second delay stages, wherein

based on a first code, the controller controls a first set of the plurality of first delay elements of one of the plurality of first delay stages or the plurality of second delay elements of one of the plurality of second delay stages to be in a first state, the first code specifying a number of the first set, and

based on a second code, greater than the first code, the controller maintains the first set of the plurality of first delay elements of one of the plurality of first delay stages or the plurality of second delay elements of one of the plurality of second delay stages in the first state and controls additional ones of the plurality of first delay elements of one of the plurality of first delay stages or the plurality of second delay elements of one of the plurality of second delay stages to be in a first state, a number of the additional ones being a difference between a number specified by the second code and the number of the first set.

14 . The device according to claim 13 , wherein the device is used in a phase locked loop (PLL).

15 . The device according to claim 14 , wherein the plurality of first delay stages are in a reference path of the PLL.

16 . The device according to claim 15 , wherein the plurality of second delay stages are in a feedback path of the PLL.

17 . The device according to claim 13 , wherein the first control state is on and the second control state is off.

18 . The device according to claim 13 , wherein the plurality of first delay elements and the plurality of second delay elements are capacitors, inverters, or varactors.