Method and apparatus for an asymmetric RF switch
An asymmetric RF switch for micro or millimeter waves, with each shunt or passthrough stack having two or more series FETs of approximately same channel width. A first lowest loss path, having only transmission line, passing through a second node, between common and first selectable ports. A second path, between the common and second selectable ports, passing through the second node, a passthrough stack, and a first node. Isolating the second selectable port from the first path by an on state of a second shunt stack connected to the first node, and an off state of the passthrough stack. Isolating the first selectable port from the second path by having an on state of the first shunt stack, or a path length, between the second node and the ground of a first shunt stack coupled to the second node, one quarter the wavelength of signals over the second path.
1 . An electronic design automation method for generating a millimeter-wave capable RF switch, comprising:
accepting input specifying whether a receive signal or a transmit signal is selected the priority signal for optimization, the unselected signal being the non-priority signal, wherein both the receive and transmit signals are millimeter waves;
accepting input specifying the transmit signal selected for the priority signal;
accepting input specifying a first power level for the receive signal and a second power level for the transmit signal;
accepting input specifying a first semiconductor process for implementation of the millimeter-wave capable RF switch;
accepting input specifying a first impedance level for the transmission lines of the millimeter-wave capable RF switch;
determining a first shunt stack peak voltage, across an off first shunt stack, and a first pass-through stack peak voltage, across an off first pass-through stack, for when the millimeter-wave capable RF switch is in transmission mode, wherein a second port of the first pass-through stack, the first shunt stack, a common port and a first selectable port are connected to a second node;
determining the first shunt stack peak voltage, and the first pass-through stack peak voltage, with use of the second power level and the first impedance level;
determining a first shunt stack number of series field effect transistors needed for the first shunt stack peak voltage;
determining a first pass-through stack number of series field effect transistors needed for the first pass-through stack peak voltage, wherein the first shunt stack number of series field effect transistors, and the first pass-through stack number of series field effect transistors are determined with use of a standoff voltage of a field effect transistor for the first semiconductor process;
determining a second shunt stack peak voltage, across an off second shunt stack, for when the millimeter-wave capable RF switch is in receive mode, wherein a first port of the first pass-through stack, the second shunt stack, and a second selectable port are connected to a first node;
determining a second shunt stack number of series field effect transistors needed for the second shunt stack peak voltage;
determining a necessary second shunt stack channel width, when the second shunt stack is on, in transmission mode for the millimeter-wave capable RF switch;
determining a necessary first shunt stack channel width, when the first shunt stack is on, and first pass-through stack channel width, when the first pass-through stack is on, in receive mode for the millimeter-wave capable RF switch is in receive mode; and
outputting the produced design for the millimeter-wave capable RF switch.
2 . The electronic design automation method of claim 1 , further comprising:
determining a gate resistor for each gate of each field effect transistor comprising the first pass-through series of field effect transistors of the first pass-through stack;
determining a resistance, for each gate resistor, sufficiently high to prevent a back current, of a first field effect transistor of the first pass-through series, from affecting the state of any other field effect transistor comprising the first pass-through series; and
determining a resistance, for each gate resistor, sufficiently low to permit the state, of any field effect transistor comprising the first pass-through series, to switch with sufficient rapidity.
3 . The electronic design automation method of claim 1 , further comprising:
determining a gate resistor for each gate of each field effect transistor comprising the first shunt series of field effect transistors of the first shunt stack;
determining a resistance, for each gate resistor, sufficiently high to prevent a back current, of a first field effect transistor of the first shunt series, from affecting the state of any other field effect transistor comprising the first shunt series; and
determining a resistance, for each gate resistor, sufficiently low to permit the state, of any field effect transistor comprising the first shunt series, to switch with sufficient rapidity.
4 . The electronic design automation method of claim 1 , further comprising:
determining a source-to-drain resistor across each source and drain of each field effect transistor comprising the first shunt series of field effect transistors of the first shunt stack;
determining a source-to-drain resistance, for each source-to-drain resistor, approximately the same as the resistance of any other source-to-drain resistor for any other field effect transistor comprising the first shunt series;
determining a resistance, for each source-to-drain resistor, sufficiently high to permit a necessary level of isolation, for the first shunt stack, when the gates of the first shunt stack receive a signal for entering the off state; and
determining a resistance, for each source-to-drain resistor, sufficiently low to permit a peak voltage, across the first shunt stack, to be sufficiently evenly divided across the first shunt series, when the gates of the first shunt stack receive a signal for entering the off state.
5 . The electronic design automation method of claim 1 further comprising:
determining a source-to-drain resistor across each source and drain of each field effect transistor comprising the first pass-through series of field effect transistors of the first pass-through stack;
determining a source-to-drain resistance, for each source-to-drain resistor, approximately the same as the resistance of any other source-to-drain resistor for any other field effect transistor comprising the first pass-through series;
determining a resistance, for each source-to-drain resistor, sufficiently high to permit a necessary level of isolation, for the first pass-through stack, when the gates of the first pass-through stack receive a signal for entering the off state; and
determining a resistance, for each source-to-drain resistor, sufficiently low to permit a peak voltage, across the first pass-through stack, to be sufficiently evenly divided, across the first pass-through series, when the gates of the first pass-through stack receive a signal for entering the off state.
6 . The electronic design automation method of claim 1 further comprising:
determining a need for power dissipation above that provided by the first shunt stack;
adding in series, between the first shunt stack and the first selectable port, a first inductor;
adding, to the side of the first inductor connected to the first selectable port, a third shunt stack; and
balancing, with the first inductor, a parasitic capacitance added by the third shunt stack and the potential of the parasitic capacitance to change transmission line impedance.
7 . The electronic design automation method of claim 1 further comprising:
determining a need for power dissipation above that provided by the second shunt stack;
adding in series, between the second shunt stack and the second selectable port, a second inductor;
adding, to the side of the second inductor connected to the second selectable port, a fourth shunt stack; and
balancing, with the second inductor, a parasitic capacitance added by the fourth shunt stack and the potential of the parasitic capacitance to change transmission line impedance.