Voltage scalable fail-safe IO drivers
A voltage driver for supplying a supply voltage includes multiple PMOS transistors, multiple NMOS transistors, a pad, impedance divider circuits, NMOS clampers, PMOS clampers, a gate protection circuit, and a bulk protection circuit. A maximum of the supply voltage is N times a maximum of the drain-source voltage of each transistor. The pad is configured to receive a voltage signal for dynamically controlling gates of a subset of the NMOS transistors and a subset of the PMOS transistors. The impedance divider circuits are configured to generate voltage signals. The NMOS clampers and PMOS clampers are configured to receive reference voltages and limited voltage signals to generate output. The gate protection circuit are between outputs of the clampers and gates of the transistors. The bulk protection circuit is between bodies of the transistors and the impedance divider circuit.
1 . A voltage driver for supplying a supply voltage (vddio), comprising:
a plurality of PMOS transistors connected in series and a plurality of NMOS transistors connected in series, each PMOS transistor of the plurality of PMOS transistors or NMOS transistor of the plurality of NMOS transistors having a drain-source voltage between a drain terminal and a source terminal (vdd), and a maximum of the supply voltage is N times a maximum of the drain-source voltage, where N>2;
a pad that receives a voltage signal (vpad) for controlling gates of a subset of the plurality of NMOS transistors and a subset of the plurality of PMOS transistors;
a first impedance divider circuit coupled to the supply voltage and the pad, the first impedance divider circuit generating a first set of voltage signals that are fractions of a voltage (padp) between the pad and vddio;
a second impedance divider circuit coupled to the pad and ground, the second impedance divider circuit generating a second set of voltage signals that are fractions of a voltage (padn) between the pad and ground;
a plurality of NMOS clampers that receive the first set of voltage signals to output a third set of voltage signals;
a plurality of PMOS clampers configured to receive the second set of voltage signals to output a fourth set of voltage signals;
a gate protection circuit coupled to outputs of the plurality of NMOS clampers and gates of a subset of the plurality of PMOS transistors respectively to protect gates of the subset of the plurality of PMOS transistors; and
a bulk protection circuit coupled to bodies of the plurality of PMOS transistors and the first impedance divider circuit to protect the bodies of the plurality of the PMOS transistors.
2 . The voltage driver of claim 1 , wherein the gate protection circuit comprises a plurality of PMOS multiplexers between the plurality of NMOS clampers and gates of a subset of the plurality of PMOS transistors.
3 . The voltage driver of claim 2 , wherein the plurality of PMOS multiplexers includes a first PMOS multiplexer that:
receives a first voltage signal and a second voltage signal different from the first voltage signal, and
selectively outputs one of the first voltage signal or the second voltage signal based on a control signal that corresponds to the supply voltage (vddio), the output of the first PMOS multiplexer connected to a gate of a first PMOS transistor of the plurality of PMOS transistors.
4 . The voltage driver of claim 3 , wherein the plurality of PMOS multiplexers includes a second PMOS multiplexer that:
receives a third voltage signal and an output of an NMOS clamper of the plurality of NMOS clampers, wherein each of the first, second, third signals is different from each other; and
selectively outputs one of the third voltage signal or the output of the NMOS clamper based on a control signal that corresponds to the second voltage signal, the output of the second PMOS multiplexer connected to a gate of a second PMOS transistor of the plurality of PMOS transistors.
5 . The voltage driver of claim 1 , wherein the bulk protection circuit comprises a plurality of PMOS clampers between bodies of the plurality of PMOS transistors and the first impedance driver.
6 . The voltage driver of claim 5 , wherein the plurality of PMOS clampers includes a first PMOS clamper that receives vddio and a first voltage signal to output a second voltage signal, and the output of the first PMOS clamper is connected to a body of a first PMOS transistor of the plurality of PMOS transistors.
7 . The voltage driver of claim 6 , wherein the plurality of PMOS clampers further includes a second PMOS clamper that receives a second voltage signal and a third voltage signal to output a fourth voltage signal, and the output of the second PMOS clamper is connected to a body of a second PMOS transistor of the plurality of PMOS transistors.
8 . The voltage driver of claim 1 , wherein the gate protection circuit is also between outputs of the plurality of PMOS clampers and gates of a subset of the plurality of NMOS transistors to protect gates of the subset of the plurality of NMOS transistors, and
wherein the bulk protection circuit is also between bodies of the plurality of NMOS transistors and the second impedance divider circuit to protect the bodies of the plurality of NMOS transistors.
9 . The voltage driver of claim 8 , wherein the gate protection circuit further comprises an NMOS multiplexer that receives two voltage signals and outputs one of the two voltage signals to a gate of one of the plurality of NMOS transistors.
10 . The voltage driver of claim 8 , wherein the bulk protection circuit further comprises a plurality of additional NMOS transistors between the bodies of a subset of the plurality of NMOS transistors and the second impedance driver.
11 . The voltage driver of claim 1 , wherein vpad swings between 0 and vddio.
12 . The voltage driver of claim 1 , wherein the plurality of PMOS transistors comprises N+1 PMOS transistors, and the plurality of NMOS transistors comprises N+1 NMOS transistors.
13 . The voltage driver of claim 1 , wherein the plurality of PMOS clampers comprises N−1 PMOS clampers, and the plurality of NMOS clampers comprises N−1 NMOS clampers.
14 . The voltage driver of claim 1 , each of the plurality of NMOS clampers comprises two interconnected NMOS transistors that receives two voltage signals and output a minimum of the two voltage signals.
15 . The voltage driver of claim 1 , each PMOS clamper of the plurality of PMOS clampers comprises two interconnected PMOS transistors that receives two voltage signals and output a maximum of the two voltage signals.
16 . The voltage driver of claim 1 , wherein the first impedance divider circuit or the second impedance divider circuit comprises N identical resistors.
17 . The voltage driver of claim 1 , wherein vrefn=vddio/N, and vrefp=(N−1)*vddio/N.
18 . The voltage driver of claim 1 , wherein the voltage signals include a signal corresponding to padp/N or multiples of padp/N.
19 . A non-transitory computer-readable storage medium having instructions encoded thereon that, when executed by a processor, cause the processor to generate a design of a voltage driver for supplying a supply voltage (vddio), the voltage driver comprising:
a plurality of PMOS transistors connected in series and a plurality of NMOS transistors connected in series, each PMOS transistor of the plurality of PMOS transistors or NMOS transistor of the plurality of NMOS transistors having a drain-source voltage between a drain terminal and a source terminal (vdd), and a maximum of the supply voltage is N times a maximum of the drain-source voltage, where N>2;
a pad that receives a voltage signal (vpad) for controlling gates of a subset of the plurality of NMOS transistors and a subset of the plurality of PMOS transistors;
a first impedance divider circuit coupled to the supply voltage and the pad, the first impedance divider circuit generating a first set of voltage signals that are fractions of a voltage (padp) between the pad and vddio;
a second impedance divider circuit coupled to the pad and ground, the second impedance divider circuit generating a second set of voltage signals that are fractions of a voltage (padn) between the pad and ground;
a plurality of NMOS clampers that receive the first set of voltage signals to output a third set of voltage signals;
a plurality of PMOS clampers configured to receive the second set of voltage signals to output a fourth set of voltage signals;
a gate protection circuit coupled to outputs of the plurality of NMOS clampers and gates of a subset of the plurality of PMOS transistors respectively to protect gates of the subset of the plurality of PMOS transistors; and
a bulk protection circuit coupled to bodies of the plurality of PMOS transistors and the first impedance divider circuit to protect the bodies of the plurality of the PMOS transistors.
20 . A system comprising:
a processor; and
a non-transitory computer-readable storage medium having instructions encoded thereon that, when executed by the processor, cause the processor to generate a design of a voltage driver for supplying a supply voltage (vddio), the voltage driver comprising:
a plurality of PMOS transistors connected in series and a plurality of NMOS transistors connected in series, each PMOS transistor of the plurality of PMOS transistors or NMOS transistor of the plurality of NMOS transistors having a drain-source voltage between a drain terminal and a source terminal (vdd), and a maximum of the supply voltage is N times a maximum of the drain-source voltage, where N>2;
a pad that receives a voltage signal (vpad) for controlling gates of a subset of the plurality of NMOS transistors and a subset of the plurality of PMOS transistors;
a first impedance divider circuit coupled to the supply voltage and the pad, the first impedance divider circuit generating a first set of voltage signals that are fractions of a voltage (padp) between the pad and vddio;
a second impedance divider circuit coupled to the pad and ground, the second impedance divider circuit generating a second set of voltage signals that are fractions of a voltage (padn) between the pad and ground;
a plurality of NMOS clampers that receive the first set of voltage signals to output a third set of voltage signals;
a plurality of PMOS clampers configured to receive the second set of voltage signals to output a fourth set of voltage signals;
a gate protection circuit coupled to outputs of the plurality of NMOS clampers and gates of a subset of the plurality of PMOS transistors respectively to protect gates of the subset of the plurality of PMOS transistors; and
a bulk protection circuit coupled to bodies of the plurality of PMOS transistors and the first impedance divider circuit to protect the bodies of the plurality of the PMOS transistors.