Phase-locked loop clock data recovery architecture
A clock data recovery circuit that uses a phase-locked loop circuit is disclosed. The clock data recovery circuit includes a phase circuit that generates a modulation signal using a recovered clock signal and an input signal that encodes multiple data symbols. A phase-locked loop circuit generates the recovered clock signal using the modulation signal and generates a feedback signal whose frequency is a non-integer factor of the of the recovered clock signal. The phase-locked loop circuit further generates the recovered clock signal using the feedback signal and a reference signal.
1 . An apparatus, comprising:
a phase circuit configured to generate a modulation signal using an input signal and a recovered clock signal, wherein the input signal encodes a plurality of data symbols; and
a phase-locked loop circuit configured to:
generate the recovered clock signal using the modulation signal;
generate a reduced frequency signal, wherein a first frequency of the reduced frequency signal is less than a second frequency of the recovered clock signal;
generate a plurality of phase signals using the reduced frequency signal;
generate, using the modulation signal, a feedback signal based on respective phases of at least two phase signals of the plurality of phase signals, wherein a ratio of respective frequencies of the feedback signal and the recovered clock signal is a non-integer value; and
modify the recovered clock signal using the feedback signal and a reference signal.
2 . The apparatus of claim 1 , wherein to generate the modulation signal, the phase circuit is further configured to:
perform a phase-frequency comparison of the input signal and the recovered clock signal to generate an error signal; and
filter the error signal to generate the modulation signal.
3 . The apparatus of claim 1 , wherein to modify the recovered clock signal, the phase-locked loop circuit is further configured to:
perform a phase-frequency comparison of the reference signal and the feedback signal to generate a phase-difference signal;
filter the phase-difference signal to generate a filtered signal; and
adjust a frequency of the recovered clock signal using the filtered signal.
4 . The apparatus of claim 3 , wherein the phase-locked loop circuit is further configured to adjust the frequency of the recovered clock signal using the filtered signal and the modulation signal.
5 . The apparatus of claim 1 , wherein to generate the feedback signal, the phase-locked loop circuit is further configured to determine a phase relationship between the feedback signal and the at least two phase signals using the modulation signal.
6 . The apparatus of claim 4 , wherein the phase-locked loop circuit includes an oscillator circuit configured to generate the recovered clock signal using the filtered signal and the modulation signal.
7 . A method, comprising:
receiving, by a phase circuit, an input signal that encodes a plurality of data symbols;
generating, by the phase circuit, a modulation signal using the input signal and a recovered clock signal;
generating, by a phase-locked loop circuit, the recovered clock signal using the modulation signal;
generating, by the phase-locked loop circuit, a reduced frequency signal, wherein a first frequency of the reduced frequency signal is less than a second frequency of the recovered clock signal;
generating, by the phase-locked loop circuit, a plurality of phase signals using the reduced frequency signal;
generating, by the phase-locked loop circuit using the modulation signal, a feedback signal based on respective phases of at least two phase signals of the plurality of phase signals, wherein a ratio of respective frequencies of the feedback signal and the recovered clock signal is a non-integer value; and
modifying, by the phase-locked loop circuit, the recovered clock signal using the feedback signal and a reference signal.
8 . The method of claim 7 , wherein generating, by the phase circuit, the modulation signal includes:
performing, by the phase circuit, a phase-frequency comparison of the input signal and the recovered clock signal to generate an error signal; and
filtering, by the phase circuit, the error signal to generate the modulation signal.
9 . The method of claim 7 , wherein modifying, by the phase-locked loop circuit, the recovered clock signal using the feedback signal and the reference signal includes:
performing, by the phase-locked loop circuit, a phase-frequency comparison of the reference signal and the feedback signal to generate a phase-difference signal;
filtering, by the phase-locked loop circuit, the phase-difference signal to generate a filtered signal; and
adjusting, by the phase-locked loop circuit, a frequency of the recovered clock signal using the filtered signal.
10 . The method of claim 9 , further comprising adjusting, by the phase-locked loop circuit, the frequency of the recovered clock signal using the filtered signal and the modulation signal.
11 . The method of claim 7 , wherein generating, by the phase-locked loop circuit, the feedback signal includes determining, by the phase-locked loop circuit, a phase relationship between the feedback signal and the at least two phase signals using the modulation signal.
12 . The method of claim 7 , further comprising sampling, by a sampler circuit using the recovered clock signal, the input signal to generate a plurality of recovered data symbols.
13 . The method of claim 10 , wherein the phase-locked loop circuit includes an oscillator circuit, and wherein adjusting the frequency of the recovered clock signal includes controlling a frequency of the oscillator circuit using the filtered signal and the modulation signal.
14 . An apparatus, comprising:
a first device configured to transmit a data signal via a communication bus, wherein the data signal encodes a plurality of data symbols; and
a second device configured to:
receive the data signal via the communication bus;
generate a modulation signal using the data signal and a recovered clock signal;
generate a reduced frequency signal, wherein a first frequency of the reduced frequency signal is less than a second frequency of the recovered clock signal;
generate a plurality of phase signals using the reduced frequency signal;
generate a feedback signal based on respective phases of at least two phase signals of the plurality of phase signals, wherein a ratio of respective frequencies of the feedback signal and the recovered clock signal is a non-integer value; and
modify the recovered clock signal using the feedback signal and a reference signal.
15 . The apparatus of claim 14 , wherein to generate the modulation signal, the second device is further configured to:
perform a phase-frequency comparison of the data signal and the recovered clock signal to generate an error signal; and
filter the error signal to generate the modulation signal.
16 . The apparatus of claim 14 , wherein to modify the recovered clock signal, the second device is further configured to:
perform a phase-frequency comparison of the reference signal and the feedback signal to generate a phase-difference signal;
filter the phase-difference signal to generate a filtered signal; and
adjust a frequency of the recovered clock signal using the filtered signal.
17 . The apparatus of claim 16 , wherein the second device is further configured to adjust the frequency of the recovered clock signal using the filtered signal and the modulation signal.
18 . The apparatus of claim 14 , wherein to generate the feedback signal, the second device is further configured to determine a phase relationship between the feedback signal and the at least two phase signals using the modulation signal.
19 . The apparatus of claim 14 , wherein the second device is further configured to sample, using the recovered clock signal, the data signal to generate a plurality of recovered data symbols.
20 . The apparatus of claim 17 , wherein the second device includes an oscillator circuit configured to generate the recovered clock signal using the filtered signal and the modulation signal.