Delay buffer unit and operating method thereof, computing device and operating method thereof

1 . A delay buffer unit, comprising: a first-stage inverter, a second-stage inverter and a delay adjustment sub-unit, wherein

an input terminal of the first-stage inverter serves as an input terminal of the delay buffer unit;

an input terminal of the second-stage inverter is connected with an output terminal of the first-stage inverter, and an output terminal of the second-stage inverter serves as an output terminal of the delay buffer unit;

the delay adjustment sub-unit is connected between a first terminal of the first-stage inverter and a first operating voltage terminal, and the delay adjustment sub-unit comprises a memristor and is configured to adjust a transmission delay of the first-stage inverter by controlling and using the memristor according to a first control signal.

2 . The delay buffer unit according to claim 1 , wherein the delay adjustment sub-unit further comprises a control switch,

the control switch comprises a first electrode, a second electrode and a control electrode, the control electrode receives the first control signal to conduct or cut off the first electrode and the second electrode according to the first control signal, the first electrode of the control switch is electrically connected with the first terminal of the first-stage inverter;

a first terminal of the memristor is electrically connected with the first electrode of the control switch and the first terminal of the first-stage inverter, and a second terminal of the memristor is electrically connected with the first operating voltage terminal.

3 . The delay buffer unit according to claim 2 , wherein the second electrode of the control switch is electrically connected with the first operating voltage terminal, or with a second operating voltage terminal that is different from the first operating voltage terminal.

4 . An operating method of the delay buffer unit according to claim 1 , comprising:

receiving an input signal of the delay buffer unit at the input terminal of the first-stage inverter, and outputting an output signal of the delay buffer unit at the output terminal of the second-stage inverter; and

receiving the first control signal by the delay adjustment sub-unit, and adjusting the transmission delay of the first-stage inverter by controlling and using the memristor according to the first control signal.

5 . The operating method according to claim 4 , wherein the delay adjustment sub-unit further comprises a control switch, the control switch comprises a first electrode, a second electrode and a control electrode, and a first terminal of the memristor is electrically connected with the first electrode of the control switch,

the receiving the first control signal by the delay adjustment sub-unit, and adjusting the transmission delay of the first-stage inverter by controlling and using the memristor according to the first control signal, comprises:

controlling whether to access the memristor between the first terminal of the first-stage inverter and the first operating voltage terminal by the control switch according to the first control signal; and

changing a source degeneracy resistance of the first-stage inverter based on the input signal by using the memristor to adjust the transmission delay of the first-stage inverter.

6 . The operating method according to claim 5 , wherein in a case where the memristor is accessed between the first terminal of the first-stage inverter and the first operating voltage terminal according to the first control signal, the transmission delay of the first-stage inverter is a transmission delay adjusted by the memristor; and

in a case where the memristor is bypassed between the first terminal of the first-stage inverter and the first operating voltage terminal according to the first control signal, the transmission delay of the first-stage inverter is an intrinsic delay of the first-stage inverter.

7 . The operating method according to claim 4 , further comprising:

disconnecting a conductive path between the delay adjustment sub-unit and the first-stage inverter according to the input signal; and

connecting the delay adjustment sub-unit with the first operating voltage terminal and a second operating voltage terminal to perform a first processing operation on the memristor according to the first control signal.

8 . The operating method according to claim 7 , wherein the delay adjustment sub-unit further comprises a control switch, the control switch comprises a first electrode, a second electrode and a control electrode, and a first terminal of the memristor is electrically connected with the first electrode of the control switch,

the connecting the delay adjustment sub-unit with the first operating voltage terminal and a second operating voltage terminal to perform a first processing operation on the memristor according to the first control signal, comprises:

connecting the second electrode of the control switch with the first operating voltage terminal, and connecting a second terminal of the memristor with the second operating voltage terminal;

turning on the control switch according to the first control signal to adjust a resistance value of the memristor by a first processing operating voltage between the first operating voltage terminal and the second operating voltage terminal.

9 . The operating method according to claim 7 , wherein the first processing operation comprises a set operation, a reset operation, a read operation or an initialization operation.

10 . A computing device, comprising:

a delay computing array, comprising 2M rows and N columns of delay buffer units, 2N word lines corresponding to the N columns, N bit lines corresponding to the N columns, and 2M source lines corresponding to the 2M rows,

wherein N delay buffer units in each of the 2M rows are connected in series to form a row of delay chain, each two adjacent rows of delay chains constitute a delay processing combination, two rows of delay chains in each delay processing combination receive a same input signal;

two delay buffer units located in a same column in each delay processing combination are respectively connected with two word lines corresponding to the same column;

each of the delay buffer units comprises a first-stage inverter, a second-stage inverter and a delay adjustment sub-unit,

an input terminal of the first-stage inverter serves as an input terminal of the delay buffer unit,

an input terminal of the second-stage inverter is connected with an output terminal of the first-stage inverter, and an output terminal of the second-stage inverter serves as an output terminal of the delay buffer unit,

the delay adjustment sub-unit is connected with a first terminal of the first-stage inverter, and is connected with a source line corresponding to a row where the delay adjustment sub-unit is located, a bit line corresponding to a column where the delay adjustment sub-unit is located, and a word line corresponding to the column where the delay adjustment sub-unit is located,

the delay adjustment sub-unit comprises a memristor, and is configured to adjust a transmission delay of the first-stage inverter by controlling and using the memristor according to a first control signal provided by a corresponding word line.

11 . The computing device according to claim 10 , wherein the delay adjustment sub-unit further comprises a control switch, the control switch comprises a first electrode, a second electrode and a control electrode,

the control electrode of the control switch is connected with the word line corresponding to the column where the delay adjustment sub-unit is located, the first electrode of the control switch is connected with the first terminal of the first-stage inverter and a first terminal of the memristor, and the second electrode of the control switch is connected with the source line corresponding to the row where the delay adjustment sub-unit is located,

wherein a second terminal of the memristor is connected with the bit line corresponding to the column where the delay adjustment sub-unit is located.

12 . The computing device according to claim 10 , further comprising:

at least one delay charge conversion module, connected with the delay processing combination, and configured to quantify a delay difference of output signals of the two rows of delay chains in the delay processing combination into a voltage output signal;

at least one analog-to-digital conversion module, connected with the delay charge conversion module, and configured to convert the voltage output signal outputted from the delay charge conversion module into a digital signal.

13 . The computing device according to claim 12 , wherein the computing device comprises a plurality of delay charge conversion modules,

the plurality of delay charge conversion modules are connected with one analog-to-digital conversion module to time-division multiplex the analog-to-digital conversion module.

14 . The computing device according to claim 10 , further comprising:

an intrinsic delay calibration module, connected with the delay processing combination, and configured to calibrate intrinsic delays of the two rows of delay chains so that the intrinsic delays of the two rows of delay chains match with each other.

15 . An operating method of a computing device according to claim 10 , comprising:

controlling at least one delay processing combination in the delay computing array through the 2N word lines according to a control signal combination, wherein the control signal combination comprises 2N first control signals that are respectively applied to the 2N word lines;

applying corresponding input signals respectively to input terminals of the at least one delay processing combination, and receiving output signals obtained by delay processing the corresponding input signals at output terminals of the at least one delay processing combination.

16 . The operating method according to claim 15 , further comprising:

for each delay buffer unit in the delay processing combination, selecting an operation mode according to the corresponding input signals, and performing an operation corresponding to the operation mode according to the control signal combination.

17 . The operating method according to claim 16 , wherein the operating mode comprises a first operating mode and a second operating mode, and the operating method further comprises:

in a first operating mode, connecting a bit line of a column where the delay buffer unit is located with a first operating voltage terminal, and connecting a source line of a row where the delay buffer unit is located with a second operating voltage terminal, and performing a first processing operation on a memristor in the delay buffer unit according to a first control signal corresponding to the delay buffer unit;

in the second operating mode, connecting the bit line of the column where the delay buffer unit is located and a source line of a row where the delay buffer unit is located with the first operating voltage terminal, and performing a computing operation or a calibration read operation on the at least one delay processing combination according to the control signal combination.

18 . The operating method according to claim 17 , wherein performing a computing operation on at least one delay processing combination as selected according to the control signal combination, comprises:

applying 2N first control signals as computing input signals to 2N delay buffer units in the at least one delay processing combination through the 2N word lines;

obtaining a differential delay computing result from an output terminal of the at least one delay processing combination.

19 . The operating method according to claim 17 , wherein performing a calibration read operation on at least one delay processing combination selected according to the control signal combination, comprises:

determining a target column in the at least one delay processing combination for performing the calibration read operation;

applying a first control signal for accessing the memristor and a first control signal for bypassing the memristor respectively to two delay buffer units in the target column in the at least one delay processing combination;

applying a first control signal for bypassing the memristor to a plurality of columns other than the target column in the at least one delay processing combination; and

obtaining a differential delay read result at the output terminal of the at least one delay processing combination.

20 . The operating method according to claim 19 , further comprising:

determining whether to perform the first processing operation on at least one memristor in the two delay buffer units on the target column according to the differential delay read result;

in the case where the differential delay reading result does not reach an expected weight value, performing the first processing operation again on the at least one memristor.