Analog-to-digital conversion device
An analog-to-digital conversion device, includes the following elements. A sensing circuit, coupled to a bit line of a memory array, and used to sense a current in the bit line to generate a bit-sequence, the bit-sequence has a form of a thermometer code to represent an analog value. A latch logic circuit, including a plurality of latches and a plurality of logic circuits to form a page buffer of the memory array, and used to generate a bit-set according to the bit-sequence, the bit-set has a form of a binary code to represent a digital value. The latches and the logic circuits are used to perform a conversion process to convert the bit-sequence into the bit-set, and the conversion process has a bit width.
1 . An analog-to-digital conversion device, comprising:
a sensing circuit, coupled to a bit line of a memory array, and used to sense a current in the bit line to generate a bit-sequence, the bit-sequence has a form of a thermometer code to represent an analog value, comprising:
a sensing amplifier, having an input end coupled to the bit line, the input end has a first node, and the first node has a first node voltage,
wherein, the sensing circuit generates the bit-sequence according to the first node voltage and a threshold voltage of the sensing amplifier,
a latch logic circuit, including a plurality of latches and a plurality of logic circuits to form a page buffer of the memory array, and used to generate a bit-set according to the bit-sequence, the bit-set has a form of a binary code to represent a digital value;
and
at least one latch element, coupled to the sensing circuit, and used to set an initial charge amount of the first node,
wherein, the latches and the logic circuits perform a conversion process to convert the bit-sequence into the bit-set, and the conversion process has a bit width.
2 . The analog-to-digital conversion device according to claim 1 , wherein the logic circuits of the latch logic circuit include an inverter and two NAND gates, and the inverter and the NAND gates execute a truth value conversion for the thermometer code and the binary code.
3 . The analog-to-digital conversion device according to claim 1 , wherein one of the latches of the latch logic circuit is coupled to an output end of the sensing amplifier to receive the bit-sequence, and another one of the latches is coupled to a data input/output path to transmit the bit-set.
4 . The analog-to-digital conversion device according to claim 1 , wherein when the first node voltage is greater than or less than the threshold voltage, the bit-sequence has a logic value “0” or a logic value “1”.
5 . The analog-to-digital conversion device according to claim 1 , wherein the sensing circuit generates the bit-sequence according to a plurality of sensing time points at which the first node voltage decreases to the threshold voltage.
6 . The analog-to-digital conversion device according to claim 5 , wherein when the bit width of the conversion process is equal to two, the sensing circuit generates the bit-sequence according to a first time point, a second time point and a third time point of the sensing time points.
7 . The analog-to-digital conversion device according to claim 6 , wherein the latch logic circuit generates two bits of least significant bits (LSB) of the bit-set by a time-to-digital conversion (TDC) mechanism according to the first time point, the second time point and the third time point.
8 . The analog-to-digital conversion device according to claim 5 , wherein when the bit width of the conversion process is greater than or equal to three, the sensing circuit generates one bit of the bit-sequence according to at least one fourth time point of the sensing time points.
9 . The analog-to-digital conversion device according to claim 8 , wherein the latch logic circuit generates at least one bit of most significant bits (MSB) of the bit-set by a successive-approximation register (SAR) mechanism according to the at least one fourth time point.
10 . The analog-to-digital conversion device according to claim 1 , wherein when the at least one latch element stores a logic value “1” or a logic value “0”, the initial charge amount of the first node increases or decreases to an equivalent charge amount.
11 . The analog-to-digital conversion device according to claim 1 , wherein the number of the at least one latch element is equal to the bit width of the conversion process minus two.
12 . The analog-to-digital conversion device according to claim 1 , wherein the first node is coupled to a second node through a capacitor, the second node has a second node voltage, and the first node voltage and the second node voltage gradually decreases according to at least one step-voltage-difference.
13 . The analog-to-digital conversion device according to claim 12 , wherein the sensing circuit generates the bit-sequence according to a difference between the first node voltage and the at least one step-voltage-difference and the threshold voltage.
14 . The analog-to-digital conversion device according to claim 13 , wherein the sensing circuit generates the bit-sequence according to a sensing time point when the first node voltage decreases to the threshold voltage.