Continuous time pipeline analog-to-digital conversion
A continuous time reconfigurable integrator is dynamically reconfigurable to facilitate real time high-resolution modification of the integrator output signal. An initial output of the integrator is evaluated to generate a coarse estimate which is then used to modify capacitive inputs to the integrator, which result in the output of a residue signal. The initial and residue outputs are individually processed by an analog-to-digital converter (ADC), such as a successive-approximation-register ADC, and digitally combined.
1 . A method for processing a sensed signal for analog-to-digital conversion (ADC), comprising:
resetting an integrator circuit such that a previous output value from the integrator circuit is no longer present at an output of the integrator circuit, wherein the integrator circuit comprises an amplifier, a resistor located between an input node of the amplifier and the input to the integrator circuit, and at least one capacitor coupled between the input node of the amplifier and an output node of the amplifier;
receiving, at an input to the integrator circuit, the sensed signal;
integrating, by the integrator circuit, the sensed signal, wherein, based on the value of the resistor, the value of the at least one capacitor, and the resetting of the integrator a transfer function of the integrator comprises a sinc transfer function that performs built-in anti-aliasing filtering at the integrator input;
evaluating an output of the integrator circuit due to the integrating to generate a single estimate of the integrated signal;
modifying the output of the integrator circuit by removing a signal portion corresponding to the single estimate from the output of the integrator circuit to create a residual signal portion; and
determining a digital value for the sensed signal based on the modified output.
2 . The method of claim 1 , wherein resetting the integrator circuit comprises shorting an electrical connection between the input node and the output node.
3 . The method of claim 2 , wherein, prior to integrating the sensed signal, the method further comprises opening the electrical connection between the input node and the output node.
4 . The method of claim 2 , further comprising, after the integrating and prior to the evaluating, opening a circuit between the resistor and the input node.
5 . The method of claim 2 , wherein the at least one capacitor comprises a first capacitor that is selectively in parallel with a second capacitor.
6 . The method of claim 5 , wherein the second capacitor has a second capacitance value that is approximately an integer multiple of a first capacitance value of the first capacitor.
7 . The method of claim 5 , wherein during the evaluating, both the first capacitor and the second capacitor are electrically connected between the input node and the output node.
8 . The method of claim 7 , wherein during the modifying, the first capacitor is electrically connected between the input node and the output node while the second capacitor is not electrically connected between the input node and the output node.
9 . The method of claim 8 , wherein the second capacitor comprises a plurality of parallel capacitors, and wherein the modifying further comprises:
determining, based on the estimate, a respective voltage value to provide from a respective voltage source of a plurality of voltage sources to a respective capacitor of the plurality of capacitors, wherein each capacitor of the plurality of capacitors is selectively connected between one of the voltage sources of the plurality of voltage sources and the input node; and
applying the respective voltage values to respective voltage sources.
10 . The method of claim 9 , wherein a capacitance of each capacitor of the plurality of capacitors is the same as the first capacitor.
11 . The method of claim 1 , wherein evaluating the output of the integrator circuit comprises providing the output of the integrator circuit to a bitwise comparator to generate a multi-bit digital value representative of the output of the integrator circuit.
12 . The method of claim 11 , wherein modifying the output of the integrator circuit based on the estimate comprises providing an additional input signal to the input based on the multi-bit digital value.
13 . The method of claim 1 , wherein determining the digital value for the sensed signal based on the modified output comprises digitally combining an initial signal portion associated with the output of the integrator circuit and the residue signal portion based on the modified output.
14 . The method of claim 13 , wherein a successive-approximation-register analog-to-digital converter outputs a digital version of the initial signal portion and a digital version of the residue signal portion, and wherein processing circuitry combines the digital version of the initial signal portion and the digital version of the residue signal portion to determine the digital value.
15 . The method of claim 1 , wherein the sensed signal is based on an output of an analog device.
16 . The method of claim 15 , wherein the analog device comprises a gyroscope, an accelerometer, pressure sensor, temperature sensor, gas sensor, microphone, fingerprint sensor, ultrasonic range finder, or ultrasonic cardiovascular sensor.
17 . A method for processing a sensed signal from one of a plurality of inertial sensors, comprising:
resetting an integrator circuit such that a previous output value from the integrator circuit is no longer present at an output of the integrator circuit, wherein the integrator circuit comprises an amplifier, a resistor located between an input node of the amplifier and an input to the integrator circuit, and at least one capacitor coupled between the input node of the amplifier and an output node of the amplifier;
switching an input node of the integrator circuit into electrical connection with the one of the plurality of inertial sensors;
receiving, at the input node of the integrator circuit, the sensed signal;
integrating, by the integrator circuit, the sensed signal, wherein, based on the value of the resistor, the value of the at least one capacitor, and the resetting of the integrator a transfer function of the integrator comprises a sinc transfer function that performs built-in anti-aliasing filtering at the integrator input;
evaluating an output of the integrator circuit due to the integrating to generate a single estimate of the integrated signal;
generating, based on the evaluating, a residual estimate associated with the sensed signal by removing the single estimate of the integrated signal from the output of the integrator circuit;
modifying a source signal provided to one or more capacitors connected to the integrator circuit based on the residual estimate; and
outputting a modified signal based on the modifying.
18 . A system for processing a sensed signal for analog-to-digital conversion, comprising:
an integrator circuit that receives and integrates the sensed signal, wherein the integrator circuit comprises:
an amplifier;
a resistor located between an input node of the amplifier and an input to the integrator circuit;
a plurality of capacitors coupled between the input node of the amplifier and an output node of the amplifier; and
reset circuitry configured to reset the integrator circuit such that a previous output value from the integrator circuit is no longer present at an output of the integrator circuit, wherein, based on the value of the resistor, the values of the plurality of capacitors, and the resetting of the integrator circuit a transfer function of the integrator comprises a sinc transfer function that performs built-in anti-aliasing filtering at the integrator input;
a comparison circuit coupled to an output of the integrator circuit, wherein the comparison circuit receives the integrated sensed signal from the output of the integrator circuit and generates a single estimate of the integrated sensed signal, and generates one or more control signals based on the single estimate of the integrated sensed signal; and
a plurality of signal sources each associated with one or more of the plurality of capacitors, wherein a respective connection between respective signal sources of the plurality of signal sources and respective capacitors of the plurality of capacitors is modified based on the one or more control signals to remove the estimate of the integrated sensed signal from the integrator circuit.