Data transmission circuit, system including the same, and data transmission method

1 . A data transmission circuit comprising:

an encoder configured to receive an input data signal and output a transition signal that indicates a transition state of the input data signal;

a first serializer that receives the transition signal;

an auxiliary driver configured to receive an output of the first serializer and drive an output node;

a second serializer that receives the input data signal; and

a main driver configured to receive an output of the second serializer and drive the output node.

2 . The data transmission circuit of claim 1 , wherein the transition signal comprises a rising signal that indicates a rising edge of the output of the first serializer, and

the encoder is further configured to generate the rising signal by comparing adjacent bits of the input data signal.

3 . The data transmission circuit of claim 1 , wherein the transition signal comprises a falling signal that indicates a falling edge of the output of the first serializer, and

the encoder is further configured to generate the falling signal by comparing adjacent bits of the input data signal.

4 . The data transmission circuit of claim 1 , wherein the encoder comprises a flip-flop configured to receive and delay a least significant bit (LSB) of the input data signal, and

the encoder is further configured to compare the delayed LSB of the input data signal with a most significant bit (MSB) of a subsequent input data signal.

5 . The data transmission circuit of claim 1 , wherein the auxiliary driver is further configured to maintain a high impedance state when there is no transition of the input data signal.

6 . The data transmission circuit of claim 1 , wherein the first serializer comprises:

a first multiplexer configured to receive the transition signal and multiplex the transition signal into an internal signal; and

a second multiplexer configured to receive the internal signal and multiplex the internal signal into a serial signal.

7 . The data transmission circuit of claim 6 , wherein the second multiplexer comprises a delay circuit configured to delay a clock signal for multiplexing the internal signal.

8 . The data transmission circuit of claim 7 , wherein the delay circuit is further configured to control a driving time of the auxiliary driver by adjusting a delay time of the clock signal.

9 . The data transmission circuit of claim 8 , wherein the delay circuit is further configured to control the driving time of the auxiliary driver to be shorter than one unit interval (UI).

10 . The data transmission circuit of claim 1 , wherein the auxiliary driver comprises:

a first pre-driver configured to receive the output of the first serializer and output a first pull-up signal and a first pull-down signal; and

a first output driver configured to output a first output signal in response to the first pull-up signal and the first pull-down signal, and

the main driver comprises:

a second pre-driver configured to receive the output of the second serializer and output a second pull-up signal and a second pull-down signal; and

a second output driver configured to output a second output signal in response to the second pull-up signal and the second pull-down signal.

11 . The data transmission circuit of claim 10 , further comprising a calibration circuit configured to output a first driving control signal for controlling a driving strength of the auxiliary driver and a second driving control signal for controlling driving strength of the main driver.

12 . A data transmission method comprising:

encoding an input data signal into a transition signal that indicates a transition state of the input data signal;

generating a first serial signal by serializing the transition signal;

driving an output node based on the first serial signal;

generating a second serial signal by serializing the input data signal; and

driving the output node based on the second serial signal,

wherein the transition signal comprises a rising signal that indicates a rising edge of the first serial signal and a falling signal that indicates a falling edge of the first serial signal.

13 . The data transmission method of claim 12 , wherein the encoding comprises comparing a first bit of the input data signal with a bit adjacent to the first bit.

14 . The data transmission method of claim 12 , wherein the generating of the first serial signal comprises:

generating an internal signal by multiplexing the rising signal and the falling signal; and

delaying a clock signal for multiplexing the internal signal, and

the delaying of the clock signal comprises controlling a driving time of an auxiliary driver based on the first serial signal by adjusting a delay time of the clock signal.

15 . The data transmission method of claim 12 , wherein the driving of the output node based on the first serial signal comprises maintaining a high impedance state when there is no transition of the input data signal.

16 . A system comprising a first device and a second device configured to communicate with the first device, wherein the first device comprises a data transmission circuit,

the data transmission circuit comprises:

an encoder configured to receive an input data signal and output a transition signal that indicates a transition state of the input data signal;

a first serializer that receives the transition signal;

an auxiliary driver that receives an output of the first serializer and is connected to an output node;

a second serializer that receives the input data signal; and

a main driver that receives an output of the second serializer and is connected to the output node, and

the second device comprises a data reception circuit configured to receive an output of the first device through the output node.

17 . The system of claim 16 , wherein the transition signal comprises a rising signal that indicates a rising edge of the output of the first serializer, and

the encoder comprises:

an XOR gate configured to receive a first bit of the input data signal and a second bit adjacent to the first bit; and

an AND gate configured to receive an output of the XOR gate and the second bit to output the rising signal.

18 . The system of claim 16 , wherein the transition signal comprises a falling signal that indicates a falling edge of the output of the first serializer, and

the encoder comprises:

an XOR gate configured to receive a first bit of the input data signal and a second bit adjacent to the first bit;

an inverter configured to receive the second bit; and

an AND gate configured to receive an output of the XOR gate and an output of the inverter to output the falling signal.

19 . The system of claim 16 , wherein the first serializer comprises:

a first multiplexer configured to receive the transition signal and multiplex the transition signal into an internal signal; and

a second multiplexer configured to receive the internal signal and multiplex the internal signal into a serial signal, and

the second multiplexer comprises at least one transistor configured to delay a clock signal for multiplexing the internal signal.

20 . The system of claim 16 , wherein the auxiliary driver comprises:

a first pre-driver configured to receive the output of the first serializer and output a first pull-up signal and a first pull-down signal;

a first pull-up transistor configured to be driven based on the first pull-up signal; and

a second pull-down transistor configured to be driven based on the first pull-down signal, and

the main driver comprises:

a second pre-driver configured to receive the output of the second serializer and output a second pull-up signal and a second pull-down signal;

a second pull-up transistor configured to be driven based on the second pull-up signal; and

a second pull-down transistor configured to be driven based on the second pull-down signal.