Radio transmitter

1 . A method, comprising:

controlling a digitally controlled oscillator to generate an output clock signal;

dividing the output clock signal to generate a first divided clock signal;

generating, in a digital-to-time converter, a first feedback clock signal based on the divided clock signal;

generating, in a time-to-digital converter, a first phase error signal based on a first bias control word and a first phase difference between a reference clock signal and the first feedback clock signal;

performing a calibration process utilizing a training sequence to generate a gain error signal;

modifying the first bias control word based on the gain error signal to generate a modified first bias control word; and

generating, in the time-to-digital converter, a second phase error signal for a second phase difference between the reference clock signal and a second feedback clock signal based on the modified first bias control word.

2 . The method of claim 1 , wherein:

the time-to-digital converter comprises:

a first chain of buffers comprising left side buffers having delays controlled by the first bias control word and right side buffers having delays controlled by the first bias control word; and

a second chain of buffers comprising left side buffers having delays controlled by a second bias control word and right side buffers having delays controlled by the second bias control word, wherein:

generating the first phase error signal comprises:

providing the reference clock signal to the right side buffers of the first chain and the left side buffers of the second chain; and

providing the first feedback clock signal to the right side buffers of the second chain and the left side buffers of the first chain.

3 . The method of claim 2 , wherein:

the second bias control word comprises a fixed value.

4 . The method of claim 2 , wherein:

the first chain of buffers and the second chain of buffers are arranged in stages;

each stage comprises:

a first buffer from one of the first chain or the first chain receiving the reference clock signal;

a second buffer from the other of the first chain or the second chain receiving the feedback clock signal; and

a latch element configured to determine which of the reference clock signal or the feedback clock signal is detected first in the stage; and

generating the first phase error signal comprises:

generating the first phase error signal based on values of the latch elements for the stages.

5 . The method of claim 4 , wherein:

the latch element comprises a time arbiter.

6 . The method of claim 1 , wherein:

performing the calibration process comprises:

differentiating and scaling the training sequence by a calibration gain to generate a scaled training sequence;

generating a second divided clock signal based on the scaled training sequence;

delaying and scaling the training sequence by the calibration gain and a nominal time-to-digital converter gain to generate a nominal scaled training sequence;

generating, in the digital-to-time converter, a third feedback clock signal based on the second divided clock signal;

generating, in the time-to-digital converter, a third phase error signal based on a third phase difference between the reference clock signal and the third feedback clock signal and the first bias control word; and

comparing the nominal scaled training sequence to the third phase error signal to generate the gain error signal.

7 . A frequency synthesizer, comprising:

a digitally controlled oscillator configured to generate an output clock signal based on a digital control word;

a clock divider configured to divide the output clock signal to generate a divided clock signal;

a digital-to-time converter configured to generate a feedback clock signal based on the divided clock signal;

a time-to-digital converter configured to generate a phase error signal based on a bias control word and a phase difference between a reference clock signal and the feedback clock signal;

a loop filter connected to the time-to-digital converter and configured to generate the digital control word based on the phase error signal; and

a calibration unit configured to:

generate a training sequence;

generate a gain error signal by utilizing the training sequence; and

modify the bias control word based on the gain error signal to generate a modified bias control word.

8 . The frequency synthesizer of claim 7 , wherein the time-to-digital converter comprises:

a first chain of buffers comprising left side buffers having delays controlled by the bias control word and right side buffers having delays controlled by the bias control word; and

a second chain of buffers comprising left side buffers having delays controlled by a second bias control word and right side buffers having delays controlled by the second bias control word, wherein:

the reference clock signal is connected to the right side buffers of the first chain and the left side buffers of the second chain; and

the feedback clock signal is connected to the right side buffers of the second chain and the left side buffers of the first chain.

9 . The frequency synthesizer of claim 8 , wherein:

the second bias control word comprises a fixed value.

10 . The frequency synthesizer of claim 8 , wherein:

the first chain of buffers and the second chain of buffers are arranged in stages;

each stage comprises:

a first buffer from one of the first chain or the first chain receiving the reference clock signal;

a second buffer from the other of the first chain or the second chain receiving the feedback clock signal; and

a latch element configured to determine which of the reference clock signal or the feedback clock signal is detected first in the stage; and

the phase error signal is generated based on values of the latch elements for the stages.

11 . The frequency synthesizer of claim 10 , wherein:

the latch element comprises a time arbiter.

12 . The frequency synthesizer of claim 11 , wherein:

the latch element comprises a flip flop connected to the time arbiter.

13 . The frequency synthesizer of claim 7 , wherein:

the calibration unit is configured to:

differentiate and scale the training sequence by a calibration gain to generate a scaled training sequence; and

delay and scale the training sequence by the calibration gain and a nominal time-to-digital converter gain to generate a nominal scaled training sequence;

the clock divider is configured to:

generate the divided clock signal based on the scaled training sequence; and

the calibration unit is configured to:

compare the nominal scaled training sequence to the phase error signal to generate the gain error signal.

14 . A radio, comprising:

an antenna port;

a transmit-receive switch connected to the antenna port;

a receive path connected to the transmit-receive switch;

a transmit path connected to the transmit-receive switch; and

a processor configured to connect the receive path to the transmit-receive switch in a receive mode of the radio and connect the transmit path to the transmit-receive switch in a transmit mode of the radio, wherein:

the transmit path comprises:

a frequency synthesizer configured to generate an output clock signal;

a local oscillator generator configured to generate a local oscillator signal based on the output clock signal; and

a power amplifier connected to the transmit-receive switch and configured to amplify the local oscillator signal to generate a transmit signal; and

the frequency synthesizer comprises:

a digitally controlled oscillator configured to generate the output clock signal based on a digital control word;

a clock divider configured to divide the output clock signal to generate a divided clock signal;

a digital-to-time converter configured to generate a feedback clock signal based on the divided clock signal;

a time-to-digital converter configured to generate a phase error signal based on a bias control word and a phase difference between a reference clock signal and the feedback clock signal;

a loop filter connected to the time-to-digital converter and configured to generate the digital control word based on the phase error signal; and

a calibration unit configured to:

generate a training sequence;

generate a gain error signal by utilizing the training sequence; and

modify the bias control word based on the gain error signal to generate a modified bias control word.

15 . The radio of claim 14 , wherein the time-to-digital converter comprises:

a first chain of buffers comprising left side buffers having delays controlled by the bias control word and right side buffers having delays controlled by the bias control word; and

a second chain of buffers comprising left side buffers having delays controlled by a second bias control word and right side buffers having delays controlled by the second bias control word, wherein:

the reference clock signal is connected to the right side buffers of the first chain and the left side buffers of the second chain; and

the feedback clock signal is connected to the right side buffers of the second chain and the left side buffers of the first chain.

16 . The radio of claim 15 , wherein:

the second bias control word comprises a fixed value.

17 . The radio of claim 15 , wherein:

the first chain of buffers and the second chain of buffers are arranged in stages;

each stage comprises:

a first buffer from one of the first chain or the first chain receiving the reference clock signal;

a second buffer from the other of the first chain or the second chain receiving the feedback clock signal; and

a latch element configured to determine which of the reference clock signal or the feedback clock signal is detected first in the stage; and

the phase error signal is generated based on values of the latch elements for the stages.

18 . The radio of claim 17 , wherein:

the latch element comprises a timer arbiter.

19 . The radio of claim 18 , wherein:

the latch element comprises a flip flop connected to the time arbiter.

20 . The radio of claim 15 , wherein:

the calibration unit is configured to:

differentiate and scale the training sequence by a calibration gain to generate a scaled training sequence; and

delay and scale the training sequence by the calibration gain and a nominal time-to-digital converter gain to generate a nominal scaled training sequence;

the clock divider is configured to:

generate the divided clock signal based on the scaled training sequence; and

the calibration unit is configured to:

compare the nominal scaled training sequence to the phase error signal to generate the gain error signal.