IP Library Granted Patent US 12700947
Granted Patent B2
US 12700947 · App. 18/735,950 · Granted Aug 4, 2026

System and method for signal optimization adjustment based on different heat source information

Inventors: Wanfen Teng (San Jose, CA); Yi-Min Yu (New Taipei City, TW); Jason Yeh (New Taipei City, TW); Chao-Lung Wei (New Taipei City, TW); Fan-Cheng Huang (New Taipei City, TW); Yi-Wen Su (New Taipei City, TW); Ting-Chu Yeh (New Taipei City, TW); Mei-Yi Huang (New Taipei City, TW)
Assignee: Super Micro Computer, Inc.
H04L1/0015H04L25/03
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Quick Facts
Patent No.
US 12700947
App. No.
18/735,950
Granted
Aug 4, 2026
Kind
B2
Abstract

The present disclosure provides a system for signal optimization adjustment based on different heat source information. The system includes a plurality of heat source measurers, a first system chip, a second system chip, an electrical interconnection, and a bit error risk evaluator. The first system chip includes a signal transmitter, and the second system chip includes a signal receiver. The second system chip provides an electrical characteristic state of the signal receiver, and a signal adjustment information of the signal transmitter and/or the signal receiver. The bit error risk evaluator performs a signal optimization adjustment for an electrical characteristic of the signal receiver according to the electrical characteristic state. The present disclosure further provides a method for signal optimization adjustment.

Claims (45)

1 . A system for signal optimization adjustment based on different heat source information, the system comprising:

a first system chip comprising a signal transmitter and a first heat source measurer configured to acquire heat source information of the first system chip;

a second system chip comprising a signal receiver and a second heat source measurer configured to acquire heat source information of the second system chip, the second system chip providing an electrical characteristic state of the signal receiver for use in evaluating a signal optimization adjustment and providing signal adjustment information for at least one of the signal transmitter and the signal receiver that is associated with the electrical characteristic state based on characteristics of a signal received from the signal transmitter;

an electrical interconnection internally connected to the first system chip and the second system chip, the electrical interconnection comprising at least one circuit board and a third heat source measurer configured to acquire heat source information of the circuit board; and

a bit error risk evaluation computer configured to:

make a determination, according to the heat source information of the first system chip, the heat source information of the second system chip, and the heat source information of the circuit board and corresponding temperature thresholds, whether the signal optimization adjustment is required; and

perform the signal optimization adjustment for an electrical characteristic of the signal receiver by adjusting at least one of the signal transmitter, the signal receiver, and a signal adjuster of the electrical interconnection according to the determination and the electrical characteristic state of the signal receiver.

2 . The system as claimed in claim 1 , further comprising:

at least one signal adjuster of the electrical interconnection that is adjusted according to the signal adjustment information,

wherein an electrical characteristic of the at least one signal adjuster is adjusted to optimize the electrical characteristic of the signal receiver.

3 . The system as claimed in claim 1 , wherein the bit error risk evaluation computer is configured to provide a risk feedback or a risk-free feedback according to heat source information collected by the first, second, and third heat source measurers and according to corresponding limit temperature or warning temperature of the first system chip, the second system chip, and the circuit board.

4 . The system as claimed in claim 1 , wherein the second system chip comprises a link trainer, and the link trainer is configured to provide the electrical characteristic state of the signal receiver and the signal adjustment information for at least one of the signal transmitter and the signal receiver; and the bit error risk evaluation computer includes a function set attached to the link trainer, and is configured to transmit signal adjustment instructions to an equalizer of the first system chip, the second system chip, or a signal adjuster of the electrical interconnection.

5 . The system as claimed in claim 4 , wherein an additional function of the link trainer comprises an activation condition or an exclusion condition for restarting a link training between the signal transmitter and the signal receiver.

6 . The system as claimed in claim 1 , wherein the electrical characteristic of the signal receiver is optimally adjusted through a console on the system; wherein by restarting the system, a signal adjustment combination of the signal transmitter and the signal receiver is updated to achieve the signal optimization adjustment.

7 . The system as claimed in claim 1 , wherein the second system chip comprises a link trainer configured to provide the electrical characteristic state of the signal receiver and the signal adjustment information for at least one of the signal transmitter and the signal receiver, and the bit error risk evaluation computer is configured to send a signal-adjustment instruction to an equalizer of the first system chip the second system chip a signal adjuster of the electrical interconnection.

8 . The system as claimed in claim 1 , further comprising:

a network module connected to an external database, the external database storing a training model of the signal adjustment information,

the network module being configured to refer to training information updated in real time, and transmit adjustment instructions of an equalizer or a signal adjuster in the system.

9 . The system as claimed in claim 1 , further comprising:

a network module connected to a database of an external system structure combination, wherein heat source information from the first, second, and third heat source measurers are associated with a training model of the external system structure combination so as to generate processed heat source information provided to the bit error risk evaluation computer for use in performing a signal optimization adjustment for the electrical characteristic of the signal receiver according to the electrical characteristic state of the signal receiver.

10 . A method for signal optimization adjustment based on different heat source information, the method comprising:

acquiring heat source information of a first system chip comprising a signal transmitter and heat source information of a second system chip comprising a signal receiver by a plurality of heat source measurers in a system;

acquiring heat source information of an electrical interconnection comprising at least one circuit board internally connected to the first system chip and the second system chip;

acquiring an electrical characteristic state of the signal receiver provided by the second system chip for use in evaluating a signal optimization adjustment, and signal adjustment information that is associated with the electrical characteristic state for at least one of the signal transmitter and the signal receiver;

evaluating the heat source information of the first system chip, the heat source information of the second system chip, and the heat source information of the circuit board to make a determination whether the signal optimization adjustment is required; and

performing the signal optimization adjustment for an electrical characteristic of the signal receiver by adjusting at least one of the signal transmitter, the signal receiver, and a signal adjuster of the electrical interconnection according to a result of the determination and the electrical characteristic state of the signal receiver.

11 . The method as claimed in claim 10 , further comprising:

optimizing the electrical characteristic of the signal receiver by adjusting an electrical characteristic of a signal adjuster of the circuit board based on the signal adjustment information.

12 . The method as claimed in claim 10 , wherein evaluating the heat source information of the first system chip, the heat source information of the second system chip, and the heat source information of the circuit board comprises:

providing a risk feedback or a risk-free feedback according to a corresponding limit or warning temperature of the first system chip, the second system chip, and the circuit board.

13 . The method as claimed in claim 10 , wherein the second system chip comprises a link trainer, the method further comprising:

sending a signal adjustment instruction to an equalizer of the first system chip, the second system chip, or a signal adjuster of the electrical interconnection, or activating link training between the signal transmitter and the signal receiver.

14 . The method as claimed in claim 10 , further comprising:

defining system structure and component information according to a geometry and material file, the system structure and component information comprising component information of the first system chip, the second system chip, and the circuit board;

initializing heating conditions of the first system chip, the second system chip, and the circuit board and heat-flow conditions of a system chassis; and

generating a mesh file or an equivalent node matrix data file.

15 . The method as claimed in claim 14 , further comprising:

generating a heat source analysis data file comprising heat source information of the first system chip, the second system chip, and the circuit board.

16 . The method as claimed in claim 14 , further comprising:

running an electrical simulation engine of a thermoelectric analysis to generate electrical characteristic states based on a thermoelectric coupling of different heat sources in individual segments so as to calculate the electrical characteristic state of the signal receiver provided by the second system chip and the signal adjustment information for at least one of the signal transmitter and the signal receiver.

17 . The method as claimed in claim 15 , wherein the system structure and component information further comprises one or more cables of the electrical interconnection, and the heat source analysis data file further comprises heat source information corresponding to the one or more cables.

18 . The method as claimed in claim 16 , wherein the thermoelectric analysis comprises electrical characteristic states of thermoelectric coupling of one or a plurality of chip package segments.

19 . The method as claimed in claim 15 , wherein the heat source analysis data file is generated by a finite volume method or a finite element method so that evaluation of the heat source information of the first system chip, second system chip, and the circuit board optimizes signal adjustment for the electrical characteristic of the signal receiver.

20 . The method as claimed in claim 14 , wherein performing the signal optimization adjustment comprises adjusting one or more impedance matches in the geometry and material file.

21 . The method as claimed in claim 14 , wherein performing the signal optimization adjustment comprises adjusting one or more trace lengths in the geometry and material file.