IP Library Granted Patent US 12701088
Granted Patent B2
US 12701088 · App. 18/137,132 · Granted Aug 4, 2026

Crossbar with dynamic selection

Inventors: Karan Gupta (Bangalore, IN); Dane Thomas Mrazek (Redwood City, CA); Nan Jiang (Sudbury, MA); Mukesh Chand Agarwal (Bangalore, IN)
Assignee: NVIDIA Corporation
H04L49/101H04L49/3018H04L49/3027H04L49/9047
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Quick Facts
Patent No.
US 12701088
App. No.
18/137,132
Granted
Aug 4, 2026
Kind
B2
Abstract

A Dynamic Destination Selection (DDS) crossbar, system for routing a packet, and a switch are provided. An illustrative DDS crossbar includes one or more adaptive routing circuits to track destination credit and port availability at a time of dispatching a packet, group multiple destinations into super destination groups, perform dynamic destination routing within a super destination group, and use the destination credit and port availability for the super destination group at the time of receiving the packet to select an output destination for the packet.

Claims (33)

1 . A Dynamic Destination Selection (DDS) crossbar, comprising:

one or more adaptive routing circuits that are to track destination credit and port availability at a time of dispatching a packet, group multiple destinations into super destination groups, perform dynamic destination routing within a super destination group, and use the destination credit and port availability for the super destination group at the time of dispatching the packet to select an output destination for the packet, wherein the one or more adaptive routing circuits comprise one or more source request queues that are maintained on a super destination group basis;

a mapper block, wherein the mapper block is connected to an output of a respective source request queue from the one or more source request queues, and wherein the mapper block maps a super destination group to multiple destination ports, based on the destination credit availability at the time of dispatching the packet; and

one or more arbiter blocks to make source-to-destination assignments for the packet.

2 . The DDS crossbar of claim 1 , wherein the one or more arbiter blocks are connected to an output of the mapper block.

3 . The DDS crossbar of claim 2 , wherein the one or more arbiter blocks make the source-to-destination assignment for the packet based on the destination port availability at the time of dispatching the packet.

4 . The DDS crossbar of claim 2 , wherein the one or more adaptive routing circuits further comprise:

a remapper block connected to an output of the one or more arbiter blocks, wherein the remapper block maps the multiple destination ports back to the super destination group.

5 . The DDS crossbar of claim 4 , wherein the remapper block triggers the packet to be removed from the respective source request queue upon processing the packet.

6 . The DDS crossbar of claim 1 , wherein the packet comprises a static destination routable packet, which can be routed to specific destination only.

7 . The DDS crossbar of claim 1 , wherein the packet comprises a dynamic destination routable packet, which can be routed to any one of the destinations in a super destination group.

8 . The DDS crossbar of claim 1 , further comprising a per-source ingress data buffer.

9 . The DDS crossbar of claim 8 , wherein the per-source ingress data buffer is virtually-output queued based on destination.

10 . The DDS crossbar of claim 1 , wherein the one or more adaptive routing circuits comprise a two-dimensional arbiter that supports routing of static destination routable packets and dynamic destination routable packets.

11 . The DDS crossbar of claim 1 , wherein the one or more adaptive routing circuits are to redetermine the destination credit and port availability on a per cycle basis.

12 . A system for dispatching a packet, comprising:

one or more adaptive routing circuits that include:

one or more source request queues that are maintained on a super destination group basis and that are to receive the packet for dispatching;

a mapper block connected to an output of a respective source request queue from the one or more source request queues, wherein the mapper block maps a super destination group to multiple destination ports;

one or more arbiter blocks that make source-to-destination assignments for the packet; and

a remapper block connected to an output of the one or more arbiter blocks, wherein the remapper block maps the multiple destination ports back to the super destination group.

13 . The system of claim 12 , wherein the mapper block is one of a plurality of mapper blocks and wherein each of the plurality of mapper blocks map different super destination groups to a respective subsets of destination ports.

14 . The system of claim 13 , wherein the remapper block is one of a plurality of remapper blocks and wherein each of the plurality of remapper blocks map the respective subset of destination ports back to the different super destination groups.

15 . The system of claim 14 , wherein the one or more arbiter blocks reside between the plurality of mapper blocks and the plurality of remapper blocks.

16 . The system of claim 14 , wherein a number of source request queues in the one or more source request queues map to different super destinations groups.

17 . A switch, comprising:

a crossbar having one or more adaptive routing circuits that are to:

hold a packet in source request queue that is maintained on a super destination group basis;

map the super destination group to a plurality of destination ports;

make a source-to-destination assignment for the packet based on destination credit and port availability at a time of receiving the packet;

remap the plurality of destination ports back to the super destination group; and

trigger release of the packet from the source request queue while also causing the packet to be transmitted to a selected destination port.

18 . The switch of claim 17 , wherein the one or more adaptive routing circuits are to redetermine the destination credit and port availability on a per cycle basis, and wherein the one or more adaptive routing circuits comprise a two-dimensional arbiter that supports routing of static destination routable packets and dynamic destination routable packets.