Speculative egress forwarding

1 . An apparatus comprising:

a first data path; and

first logic associated with an ingress port and to:

in response to determining that a packet received by the ingress port is eligible for transfer from the ingress port to an egress port via the first data path, copy the packet and store the copied packet in a buffer;

segment the packet into a plurality of segments, each segment having an associated sequence number;

transfer, via the ingress port, the plurality of segments of the packet to the egress port via the first data path;

receive, from the egress port, an indication of which sequence numbers were received by the egress port;

validate transfer of the packet from the ingress port to the egress port via the first data path when the sequence numbers received from the egress port match the sequence numbers sent by the ingress port; and

in response to the validation, delete the copied packet from the buffer.

2 . The apparatus of claim 1 , wherein

the first data path is a low latency data path.

3 . The apparatus of claim 1 , wherein the first logic is to further:

place a descriptor corresponding to the packet in a descriptor queue; and

remove the descriptor from the descriptor queue in response to validating the transfer of the packet.

4 . The apparatus of claim 1 , wherein the plurality of segments are transferred to the egress port by bypassing a descriptor queue.

5 . The apparatus of claim 1 , further comprising:

a second data path, wherein the first logic is to further:

invalidate the transfer of the packet from the ingress port to the egress port when the sequence numbers at the egress port do not match the sequence numbers sent by the ingress port; and

transfer the plurality of segments to the egress port via the second data path.

6 . The apparatus of claim 5 , wherein the plurality of segments are transferred via the second data path by reading a descriptor of the packet.

7 . The apparatus of claim 1 , further comprising:

a crossbar circuit that comprises the first data path, wherein the plurality of segments are transferred via the first data path in response to receiving an indication of a congestion state of the crossbar circuit.

8 . The apparatus of claim 1 , further comprising:

at least one state machine, wherein the plurality of segments are transferred via the first data path based on a state provided by the at least one state machine.

9 . The apparatus of claim 1 , wherein the first logic is to further:

determine a buffer usage of a data buffer,

wherein the plurality of segments are transferred via the first data path based on a result of comparing the buffer usage to a threshold buffer usage value.

10 . The apparatus of claim 1 , wherein the first logic is to transfer the plurality of segments to the egress port via a second data path in response to:

a failure associated with the transfer of the plurality of segments to the egress port via the first data path; and

confirmation of at least one of:

a return of the sequence numbers to the ingress port;

a target packet count associated with the egress port; or

both.

11 . A switching device comprising:

a plurality of ingress ports;

a plurality of egress ports;

at least one switching circuit that connects the plurality of ingress ports with the plurality of egress ports, the at least one switching circuit comprising a first data path; and

first logic associated with an ingress port of the plurality of ingress ports and to:

in response determining that a packet received by the ingress port is eligible for transfer from the ingress port to an egress port of the plurality of egress ports via the first data path, copy the packet and store the copied packet in a buffer;

segment the packet received at the ingress port into a plurality of segments;

transfer, via the ingress port, the plurality of segments to the egress port via the first data path;

receive, from the egress port, an indication of which sequence numbers were received by the egress port;

validate transfer of the packet from the ingress port to the egress port via the first data path when the sequence numbers received from the egress port match the sequence numbers sent by the ingress port; and

in response to the validation, delete the copied packet from the buffer.

12 . The switching device of claim 11 , wherein

the first data path is a low latency data path.

13 . The switching device of claim 11 , wherein the first logic is to further:

place a descriptor corresponding to the packet in a descriptor queue; and

remove the descriptor from the descriptor queue in response to validating the transfer of the packet.

14 . The switching device of claim 11 , wherein the first logic is to further:

invalidate the transfer of the packet from the ingress port to the egress port when the sequence numbers at the egress port do not match the sequence numbers sent by the ingress port; and

transfer the plurality of segments to the egress port via a second data path comprised in the at least one switching circuit.

15 . The switching device of claim 11 , wherein the plurality of segments are transferred via the first data path in response to an indication of a congestion state of the at least one switching circuit.

16 . The switching device of claim 11 , further comprising:

at least one first state machine associated with the ingress port; and

at least one second state machine associated with the egress port;

wherein the plurality of segments are transferred via the first data path based on a state provided by the at least one first state machine, a state provided by the at least one second state machine, or both.

17 . An apparatus comprising:

at least one crossbar circuit comprising a low latency data path; and

first logic associated with an ingress port and to:

in response determining that a packet received by the ingress port is eligible for transfer from the ingress port to an egress port via the low latency data path, copy the packet and store the copied packet in a buffer;

transfer, from the ingress port, a plurality of segments of the packet to the egress port via the low latency data path;

receive, from the egress port, an indication of which sequence numbers were received by the egress port;

validate transfer of the packet from the ingress port to the egress port via the low latency data path when the sequence numbers received from the egress port match the sequence numbers sent by the ingress port; and

in response to the validation, delete the copied packet from the buffer.

18 . The apparatus of claim 17 , wherein the first logic is to further:

place a descriptor corresponding to the packet in a descriptor queue; and

in response to validating the transfer of the packet,

remove the descriptor from the descriptor queue.

19 . The apparatus of claim 17 , wherein the plurality of segments are transferred to the egress port by bypassing a descriptor queue.

20 . The apparatus of claim 17 , wherein the first logic is to further:

invalidate the transfer of the packet from the ingress port to the egress port when the sequence numbers at the egress port do not match the sequence numbers sent by the ingress port; and

transfer the plurality of segments to the egress port via a data path, different than the low latency data path, within the at least one crossbar circuit.