Semiconductor digital photomultiplier photon counter and imager and related technology

1 . A breakdown-avalanche photon sensors array, which is implemented in CMOS (complementary metal-oxide semiconductor) technology, wherein the breakdown-avalanche photon sensors array has single photon sensitivity, comprising:

a semiconductor substrate; and

an epitaxial layer, which is located above the semiconductor substrate; and

a breakdown-avalanche photon sensor, which is located within the epitaxial layer, wherein the breakdown-avalanche photon sensor comprises:

a guard ring;

a lower layer and an upper layer within the epitaxial layer, which form a sensitive breakdown-avalanche pn-junction, wherein the guard ring is located within the epitaxial layer;

wherein the guard ring is configured for suppression of a breakdown-avalanche process at edges of the breakdown-avalanche photon sensor due to a weaker electric field near a guard ring area compared to an electric field within a central region of the pn-junction; and

a quenching element, which is electrically connected to an area of the pn-junction of the breakdown-avalanche photon sensor, wherein the quenching element is configured for quenching the breakdown-avalanche photon sensor after detection of a photon.

2 . The breakdown-avalanche photon sensors array according to claim 1 , wherein the breakdown-avalanche photon sensors array further comprises:

optical protection trenches, wherein at least one optical protection trench is located around the photosensitive area of at least one breakdown-avalanche photon sensor of the breakdown-avalanche photon sensors array and wherein the trenches are configured to suppress optical crosstalk.

3 . The breakdown-avalanche photon sensors array according to claim 2 , wherein the photosensitive area defines an upper end of the breakdown-avalanche photon sensor in at least a portion of the breakdown-avalanche photon sensors array, and wherein at least one of the optical protection trenches extend further from the upper end than a pn-junction of the breakdown-avalanche photon sensor.

4 . A digital breakdown-avalanche photon sensor, comprising:

a breakdown-avalanche photon sensor comprising:

a guard ring;

a lower layer and an upper layer within the epitaxial layer, which form a sensitive breakdown-avalanche pn-junction, wherein the guard ring is located within the epitaxial layer;

wherein the guard ring is configured for suppression of a breakdown-avalanche process at edges of the breakdown-avalanche photon sensor due to a weaker electric field near a guard ring area compared to an electric field within a central region of the pn-junction; and

a quenching element, which is electrically connected to an upper area of the pn-junction of the breakdown-avalanche photon sensor, wherein the quenching element is configured for quenching the breakdown-avalanche photon sensor after detection of a photon; and

a digital memory, wherein the memory is electrically connected to the breakdown-avalanche photon sensor, and

wherein, upon photo detection by the breakdown-avalanche photon sensor, the breakdown-avalanche photon sensor is configured to generate a signal and send the signal to the digital memory, and

wherein the digital memory is configured to store the signal as data information.

5 . The digital breakdown-avalanche photon sensor according to claim 4 , further comprising a discriminator, which is configured to perform digitalization of the signal generated by the breakdown-avalanche photon sensor and wherein the discriminator is further configured to send the digitalized signal to the digital memory.

6 . The digital breakdown-avalanche photon sensor according to claim 5 , wherein the breakdown-avalanche photon sensor, the discriminator and the digital memory are implemented within an epitaxial layer on a substrate using CMOS (complementary metal-oxide semiconductor) technology.

7 . A digital breakdown-avalanche photon sensors array, comprising:

at least a one-dimensional array of digital breakdown avalanche photon sensors comprising:

a breakdown-avalanche photon sensor, wherein the breakdown-avalanche photon sensor comprises:

a guard ring;

a lower layer and an upper layer within the epitaxial layer, which form a sensitive breakdown-avalanche pn-junction, wherein the guard ring is located within the epitaxial layer;

wherein the guard ring is configured for suppression of a breakdown-avalanche process at edges of the breakdown-avalanche photon sensor due to a weaker electric field near a guard ring area compared to an electric field within a central region of the pn-junction; and

a quenching element, which is electrically connected to an area of the pn-junction of the breakdown-avalanche photon sensor, wherein the quenching element is configured for quenching the breakdown-avalanche photon sensor after detection of a photon; and

a digital memory, wherein the memory is electrically connected to the breakdown-avalanche photon sensor, and

wherein, upon photo detection by the breakdown-avalanche photon sensor, the breakdown-avalanche photon sensor is configured to generate a signal and send the signal to the digital memory,

wherein the digital memory is configured to store the signal as data information; and

wherein processing electronics of the digital breakdown avalanche photon sensors array are electrically connected with each other.

8 . The digital breakdown-avalanche photon sensors array according to claim 7 , wherein the processing electronics of the digital breakdown-avalanche photon sensors array are implemented within an epitaxial layer on a substrate in accordance with CMOS (complementary metal-oxide semiconductor) technology.

9 . The digital breakdown-avalanche photon sensors array according to claim 7 , further comprising

digital processing electronics providing as output information a number of photons detected at a particular time;

wherein the digital breakdown-avalanche photon sensors array is a digital photomultiplier photon counter.

10 . A digital photomultiplier imager comprising:

a digital breakdown-avalanche photon sensors array according to claim 7 ; and

processing electronics, which are electrically connected to the digital breakdown-avalanche photon sensors array and wherein the processing electronics are configured to read data information and address information from digital memories of the digital breakdown-avalanche photon sensors array, and send it to a digital output unit, which is electrically connected to the digital breakdown-avalanche photon sensors array, and wherein the digital output unit is configured to store data information and address information read from memory by the processing electronics of the digital breakdown-avalanche photon sensors array.

11 . The digital photomultiplier Imager according to claim 10 , wherein the digital processing electronics comprise:

a digital address unit, which is communicatively coupled with the digital breakdown-avalanche photon sensors array and wherein the digital address unit is configured to determine address information of processing electronics in the digital breakdown-avalanche photon sensors array; and

digital processing electronics, which are configured to control the process of reading and transferring data information from the digital breakdown-avalanche photon sensors array corresponding to determined address information,

wherein the digital address units and the digital breakdown-avalanche photon sensors array are electrically connected with each other.

12 . The digital photomultiplier Imager according to claim 10 , wherein the processing electronics further comprises:

at least one digital row decoder unit, wherein the digital row decoder unit is electrically connected to rows of the digital breakdown-avalanche photon sensors array; and

at least one digital column decoder unit, wherein the digital column decoder unit is electrically connected to columns of the digital breakdown-avalanche photon sensors array, and

wherein the digital processing electronics are electrically connected to the at least one digital row decoder unit and to the at least one digital column decoder circuit, and wherein the digital processing electronics are configured to send a reading signal to the digital row decoder and digital column decoder units corresponding to determined address information, and

wherein, upon sending the reading signal, the digital row decoder unit is configured to send a row strobe signal according to determined address information to the digital breakdown-avalanche photon sensors array and the digital column decoder unit is configured to send a column strobe signal according to determined address information to the digital breakdown-avalanche photon sensors array.

13 . The digital photomultiplier Imager according to claim 10 , wherein the processing electronics are configured to read data information from at least two memories.

14 . The digital photomultiplier Imager according to claim 10 , wherein the output unit is configured to suppress a dark rate within the epitaxial layer.

15 . The digital photomultiplier Imager according to claim 10 , wherein the processing electronics and the output unit are implemented within the epitaxial layer in accordance with CMOS (complementary metal-oxide semiconductor) technology.