Solid-state imaging element and electronic equipment including shared pixel units
Provided is a solid-state imaging element that includes shared pixel units that are disposed adjacent to each other in a horizontal direction and configured to allow a plurality of pixels to share an FD section and an amplification transistor. The shared pixel units each include a first selection transistor and a second selection transistor. The first selection transistor connects the amplification transistor to a first vertical signal line which is used when pixel signals are outputted independently for each of the pixels. The second selection transistor connects the amplification transistor to a second vertical signal line which is used when source follower addition is performed to output the pixel signals.
1 . A solid-state imaging element, comprising:
a plurality of pixel units in a horizontal direction, wherein
a first pixel unit of the plurality of pixel units is adjacent to a second pixel unit of the plurality of pixel units in the horizontal direction,
the first pixel unit includes:
a plurality of pixels;
a Floating Diffusion (FD) section;
an amplification transistor, wherein the plurality of pixels is configured to share the FD section and the amplification transistor;
a first selection transistor configured to connect the amplification transistor to a first vertical signal line,
wherein the first vertical signal line is configured to output a plurality of pixel signals from the plurality of pixels, in a case where each pixel signal of the plurality of pixel signals is outputted independently for each of the plurality of pixels; and
a second selection transistor configured to connect the amplification transistor to a second vertical signal line,
the second vertical signal line is configured to output the plurality of pixel signals, in a case where the plurality of pixel signals are added based on a source follower addition process, and a third pixel unit of the plurality of the pixel units includes:
a dummy transistor in place of the first selection transistor; and
a third selection transistor in place of the second selection transistor, wherein
in the case where the each pixel signal of the plurality of pixel signals is outputted independently for the each of the plurality of pixels, the third selection transistor is driven same as the first selection transistor, and
in the case where the plurality of pixel signals are added based on the source follower addition process, the third selection transistor is driven same as the second selection transistor.
2 . The solid-state imaging element according to claim 1 , wherein
a plurality of transistors in each of the first pixel unit and the second pixel unit is in a mirror-symmetrical arrangement in the horizontal direction, and
the plurality of transistors includes each of the amplification transistor, the first selection transistor, and the second selection transistor.
3 . The solid-state imaging element according to claim 2 , wherein
the plurality of pixels is in a 2×2 array, and
the second vertical signal line is at a center of a space between the first pixel unit and the second pixel unit, and
the first vertical signal line is outside of the space between the first pixel unit and the second pixel unit.
4 . The solid-state imaging element according to claim 2 , further comprising an on-chip lens for the each of the plurality of pixels, wherein
the plurality of pixel units is in a 2×2 array,
the plurality of pixels is in the 2×2 array, and
the plurality of pixel units is in a planar layout in which the plurality of pixel units in a vertical direction has same transistor arrangement of the plurality of transistors.
5 . The solid-state imaging element according to claim 2 , further comprising an on-chip lens for the plurality of pixels, wherein
the plurality of pixel units is in a 2×2 array,
the plurality of pixels is in the 2×2 array, and
the plurality of pixel units is in a planar layout in which the plurality of transistors is in the mirror-symmetrical arrangement in a vertical direction.
6 . The solid-state imaging element according to claim 1 , further comprising a sub-FD section configured to connect to the FD section via a connection transistor.
7 . An electronic equipment, comprising:
a solid-state imaging element that includes a plurality of pixel units, wherein
a first pixel unit of the plurality of pixel units is adjacent to a second pixel unit of the plurality of pixel units in the horizontal direction,
the first pixel unit includes:
a plurality of pixels;
a Floating Diffusion (FD) section;
an amplification transistor, wherein the plurality of pixels is configured to share the FD section and the amplification transistor;
a first selection transistor configured to connect the amplification transistor to a first vertical signal line,
wherein the first vertical signal line is configured to output a plurality of pixel signals from the plurality of pixels, in a case where each pixel signal of the plurality of pixel signals is outputted independently for each of the plurality of pixels; and
a second selection transistor configured to connect the amplification transistor to a second vertical signal line,
the second vertical signal line is configured to output the plurality of pixel signals, in a case where the plurality of pixel signals are added based on a source follower addition process, and a third pixel unit of the plurality of the pixel units includes:
a dummy transistor in place of the first selection transistor; and
a third selection transistor in place of the second selection transistor, wherein
in the case where the each pixel signal of the plurality of pixel signals is outputted independently for the each of the plurality of pixels, the third selection transistor is driven same as the first selection transistor, and
in the case where the plurality of pixel signals are added based on the source follower addition process, the third selection transistor is driven same as the second selection transistor.