IP Library Granted Patent US 12701670
Granted Patent B2
US 12701670 · App. 18/649,102 · Granted Aug 4, 2026

Riser as a bridge between add-in cards of an information handling system

Inventors: Kevin Mundt (Livingston, TX); Stephen Strickland (Foxborough, MA); Anand Nunna (Round Rock, TX)
Assignee: Dell Products L.P.
H05K7/1461G06F1/183
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Quick Facts
Patent No.
US 12701670
App. No.
18/649,102
Granted
Aug 4, 2026
Kind
B2
Abstract

An information handling system includes first and second add-in cards and a riser printed circuit board (PCB). The first add-in card is configured to connect with a host system of the information handling system via a direct connection. The riser PCB includes first and second connectors. The first add-in card is in electrical communication with the riser PCB via the first connector. The second add-in card is in electrical communication with the riser PCB via the second connector. The first and second add-in cards are configured to communicate with each other via the first and second connectors and routing on the riser PCB.

Claims (28)

1 . An information handling system comprising:

first and second add-in cards, the first add-in card to connect with a host system of the information handling system via a direct connection; and

a riser printed circuit board (PCB) including first and second connectors, the first add-in card in electrical communication with the riser PCB via the first connector, and the second add-in card in electrical communication with the riser PCB via the second connector, wherein the first and second add-in cards to communicate with each other via the first and second connectors and routing on the riser PCB, wherein the second add-in card to communicate with the host system via the first and second connectors, routing on the riser PCB, and the direct connection from a third connector on the first add-in card to the host system.

2 . The information handling system of claim 1 , wherein the first add-in card includes a third connector, wherein the first add-in card is to communicate with the host system via the third connector and a cable.

3 . The information handling system of claim 2 , wherein the third connector and the cable include multiple peripheral interconnect express lanes.

4 . The information handling system of claim 1 , wherein the riser PCB is to provide power to the first add-in card via the first connector and provide the power to the second add-in card via the second connector.

5 . The information handling system of claim 1 , wherein the first and second connectors on mounted on a same surface of the riser PCB.

6 . The information handling system of claim 1 , wherein the first and second connectors on mounted on opposite surfaces of the riser PCB.

7 . The information handling system of claim 1 , wherein the first add-in card is a field programmable gate array card.

8 . The information handling system of claim 7 , wherein the second add-in card is a system on a chip card.

9 . A method comprising:

providing, via first and second connectors on a riser printed circuit board (PCB) of an information handling system, a first communication from a first add-in card of the information handling system to a second add-in card of the information handling system;

providing, via a direct link from a third connector on the first add-in card, a second communication from the first add-in card to a host system of the information handling system; and

providing, via the first and second connectors on the riser PCB and the direct link of the third connector on the first add-in card, a third communication from the second add-in card to the host system of the information handling system.

10 . The method of claim 9 , the providing of the first communication includes: routing the first communication through a routing on the riser PCB.

11 . The method of claim 9 , further comprise: providing, via the riser PCB, power to both of the first and second add-in cards.

12 . The method of claim 9 , wherein only the first add-in card has a direct link to the host system of the information handling system.

13 . The method of claim 9 , wherein a direct link is via a peripheral component interconnect express cable.

14 . The method of claim 9 , wherein the first add-in card is a field programmable gate array card.

15 . The method of claim 14 , wherein the second add-in card is a system on a chip card.

16 . An information handling system comprising:

a riser printed circuit board (PCB) including first and second connectors;

a first add-in card including a third connector, the first add-in card in electrical communication with the riser PCB via the first connector, wherein the first add-in card is to connect with a host system of the information handling system via a direct connection through the third connector; and

a second add-in card in electrical communication with the riser PCB via the second connector, wherein the first and second add-in cards to communicate with each other via the first and second connectors and routing on the riser PCB, wherein the second add-in card to communicate with the host system via the first and second connectors, routing on the riser PCB, and the third connector, wherein the first and second add-in cards are in a first configuration when the first and second connectors on mounted on a same surface of the riser PCB, wherein the first and second add-in cards are in a second configuration when the first and second connectors on mounted on opposite surfaces of the riser PCB.

17 . The information handling system of claim 16 , wherein the third connector and a cable include multiple peripheral interconnect express lanes.

18 . The information handling system of claim 16 , wherein the riser PCB is to provide power to the first add-in card via the first connector and provide the power to the second add-in card via the second connector.

19 . The information handling system of claim 16 , wherein the first add-in card is a field programmable gate array card.

20 . The information handling system of claim 19 , wherein the second add-in card is a system on a chip card.