Integrated circuit device and method of manufacturing the same

1 . A method of manufacturing an integrated circuit device, the method comprising:

forming a plurality of lower electrodes above a substrate;

forming a dielectric film on the plurality of lower electrodes;

forming a doped upper interface film on the dielectric film; and

forming an upper electrode on the doped upper interface film,

wherein the doped upper interface film includes a dopant, and

the dopant includes one selected from tin (Sn), molybdenum (Mo), niobium (Nb), tantalum (Ta), and aluminum (Al),

the doped upper interface film is formed by alternately performing a first atomic layer deposition process and a second atomic layer deposition process,

the first atomic layer deposition process includes a first cycle of supplying and purging a base precursor, supplying and purging a dopant precursor, and supplying and purging a reactant, and

the second atomic layer deposition process includes a second cycle of supplying and purging the base precursor and supplying and purging the reactant.

2 . The method of claim 1 , wherein the doped upper interface film includes, as a base material, one selected from InO x , TiO x , SnO x , and ZnO x .

3 . The method of claim 2 , wherein the doped upper interface film corresponds to a transparent electrode.

4 . The method of claim 1 , wherein

the first atomic layer deposition process is repeatedly performed A times in a first process,

the second atomic layer deposition process is repeatedly performed B times in a second process, and

the forming the doped upper interface film includes repeatedly performing C times the first process and the second process,

where each of A, B, and C is a natural number.

5 . The method of claim 1 , wherein

the second atomic layer deposition process is repeatedly performed A times in a first process,

the first atomic layer deposition process is repeatedly performed B times in a second process, and

the forming the doped upper interface film includes repeatedly performing C times the first process and the second process,

where each of A, B, and C is a natural number.

6 . The method of claim 1 , wherein

a thickness of the doped upper interface film is less than a thickness of the dielectric film, and

the thickness of the doped upper interface film is less than or equal to 1 nm.

7 . The method of claim 1 , wherein the doped upper interface film has a work function greater than 4 eV.

8 . A method of manufacturing an integrated circuit device, the method comprising:

forming a plurality of lower electrodes above a substrate;

forming a supporter configured to support the plurality of lower electrodes;

forming a dielectric film on the plurality of lower electrodes and the supporter;

forming a doped upper interface film on the dielectric film; and

forming an upper electrode on the doped upper interface film,

wherein the doped upper interface film includes one selected from InO x doped with tin (Sn), TiO x doped with niobium (Nb), SnO x doped with tantalum (Ta), TiO x doped with Ta, and TiO x doped with molybdenum (Mo),

the doped upper interface film is formed by alternately performing a first atomic layer deposition process and a second atomic layer deposition process,

the first atomic layer deposition process includes a first cycle of supplying and purging a base precursor, supplying and purging a dopant precursor, and supplying and purging a reactant, the first cycle being performed multiple times, and

the second atomic layer deposition process includes a second cycle of supplying and purging the base precursor and supplying and purging the reactant, the second cycle being performed multiple times.

9 . The method of claim 8 , wherein the doped upper interface film corresponds to a transparent electrode having a work function greater than 4 eV.

10 . A method of manufacturing an integrated circuit device, the method comprising:

forming an isolation film defining an active region in a substrate;

forming a gate structure crossing the active region and extending in a first direction;

forming a source/drain in the active region at opposite sides of the gate structure, respectively;

forming a bit line structure extending in a second direction that is perpendicular to the first direction;

forming a plurality of contact structures on the source/drain, respectively;

forming a plurality of lower electrodes on the plurality of contact structures, respectively;

forming a supporter configured to support the plurality of lower electrodes;

forming a dielectric film on the plurality of lower electrodes and the supporter;

forming a doped upper interface film on the dielectric film; and

forming an upper electrode on the doped upper interface film,

wherein the doped upper interface film includes a dopant,

the dopant includes one selected from tin (Sn), molybdenum (Mo), niobium (Nb), tantalum (Ta), and aluminum (Al),

the doped upper interface film is formed by alternately performing a first atomic layer deposition process and a second atomic layer deposition process,

the first atomic layer deposition process includes a first cycle of supplying and purging a base precursor, supplying and purging a dopant precursor, and supplying and purging a reactant, the first cycle being performed multiple times, and

the second atomic layer deposition process includes a second cycle of supplying and purging the base precursor and supplying and purging the reactant, the second cycle being performed multiple times.

11 . The method of claim 10 , wherein the doped upper interface film includes one selected from Sn-doped InO x , Nb-doped TiO x , Ta-doped SnO x , Ta-doped TiO x , and Mo-doped TiO x .

12 . The method of claim 10 , wherein the doped upper interface film corresponds to a transparent electrode having a work function greater than 4 eV.