Semiconductor device and method for fabricating the same
A semiconductor device includes: a plurality of word line pad portions that are stacked over a lower structure in a direction perpendicular to a surface of the lower structure; horizontal-level dielectric layers between the word line pad portions; and bridge prevention layers disposed between the word line pad portions and covering ends of the horizontal-level dielectric layers.
1 . A semiconductor device, comprising:
N word line pad portions stacked over a lower structure in a direction perpendicular to a surface of the lower structure;
dielectric layers disposed between the word line pad portions; and
bridge prevention layers disposed between the word line pad portions and covering ends of the dielectric layers,
wherein the word line pad portions include an i th word line pad portion and an (i+1) th word line pad portion directly stacked over the i th word line pad portion, where i is an integer from 1 to N−1;
wherein each of the i th and (i+1) th word line pad portions includes a lower-level word line and an upper-level word line formed over the lower-level word line,
each of the bridge prevention layers covers a first lateral side of the lower-level word line of included in the (i+1) th word line pad portion and the first lateral side of the upper-level word line of included in the i th word line pad portion.
2 . The semiconductor device of claim 1 , wherein the word line pad portions include a stepped structure.
3 . The semiconductor device of claim 1 , wherein the bridge prevention layers are disposed at respective ends of the word line pad portions.
4 . The semiconductor device of claim 1 , wherein ends of the word line pad portions have a step shape.
5 . The semiconductor device of claim 1 , wherein the bridge prevention layers include a dielectric material.
6 . The semiconductor device of claim 1 , wherein each of the (i+1) th and i th word line pad portions further includes a pad including a metal-based material and disposed between the upper-level word line and the lower-level word line.
7 . The semiconductor device of claim 6 , wherein an end of the pad has a shape that protrudes beyond ends of the upper-level and lower-level word lines.
8 . The semiconductor device of claim 6 , wherein the pad is thicker than the upper-level and lower-level word lines.
9 . The semiconductor device of claim 1 , further comprising:
a passivation layer that covers respective ends of the word line pad portions and the bridge prevention layers.
10 . The semiconductor device of claim 9 , wherein the bridge prevention layers and the passivation layer include the same material.
11 . The semiconductor device of claim 1 , wherein each of the upper-level and lower-level word lines includes a plurality of segments arranged in the direction perpendicular to the surface of the lower structure.
12 . The semiconductor device of claim 11 , further comprising:
additional bridge prevention layers alternately arranged between the segments.
13 . The semiconductor device of claim 1 , wherein the bridge prevention layers cover an end of the upper-level and lower-level word lines.
14 . The semiconductor device of claim 1 , wherein the bridge prevention layers include silicon nitride (SiN).
15 . The semiconductor device of claim 1 , wherein the lower-level word line included in the (i+1) th word line pad portion is formed over the upper-level word line included in the i th word line pad portion.
16 . A semiconductor device, comprising:
a word line stack including a plurality of word lines stacked over a lower structure in a direction perpendicular to a surface of the lower structure;
N word line pad portions defined at an end of the word line stack;
dielectric layers disposed between the word line pad portions;
bridge prevention layers disposed between the word line pad portions and covering ends of the dielectric layers; and
contact plugs respectively coupled to the word line pad portions,
wherein the N word line pad portions include an i th word line pad portion and an (i+1) th word line pad portion directly stacked over the i th word line pad portion, where i is an integer from 1 to N−1;
wherein each of the i th and (i+1) th word line pad portions includes a lower-level word line and an upper-level word line formed over the lower-level word line,
each of the bridge prevention layers covers a first lateral side of the lower-level word line included in the (i+1) th word line pad portion and the first lateral side of the upper-level word line included in the i th word line pad portion.
17 . The semiconductor device of claim 16 , wherein the word line pad portions include a stepped structure.
18 . The semiconductor device of claim 16 , wherein the bridge prevention layers are disposed at ends of the word line pad portions.
19 . The semiconductor device of claim 16 , wherein ends of the word line pad portions have a step shape.
20 . The semiconductor device of claim 16 , wherein the bridge prevention layers include a dielectric material.
21 . The semiconductor device of claim 16 , wherein each of the (i+1) th and i th word line pad portions further includes a pad including a metal-based material, and disposed between the upper-level word line and the lower-level word line.
22 . The semiconductor device of claim 16 , further comprising:
a passivation layer that covers respective ends of the word line pad portions and the bridge prevention layers.
23 . The semiconductor device of claim 16 , further comprising:
active layers extending in a direction crossing the word lines;
a bit line commonly coupled to one side of the active layers and extending perpendicularly to the lower structure; and
a capacitor coupled to another side of each of the active layers.