Memory device including structures in memory array region and periperal circuitry region

1 . An apparatus comprising:

data lines;

first structures located in a first region of the apparatus, the first structures electrically separated from each other and including first conductive contacts coupled to the data lines;

second conductive contacts located in the first region and coupled to memory elements of the apparatus;

second structures located in a second region of the apparatus, the second structures electrically separated from each other and including respective gates of transistors in the second region, the second region including a portion of a semiconductor substrate, the portion of the semiconductor substrate including a source and a drain of a transistor among the transistors, wherein the gates include a conductive material formed over the portion of the semiconductor substrate including the source and the drain of the transistor, and the conductive material is separated from the source and the drain of the transistor;

a first dielectric material formed in the second region, the first dielectric material including a first portion and a second portion, the first portion formed at a first side of a structure among the second structures, the second portion formed at a second side first of the structure; and

a second dielectric material formed over the first structures and the second structures, wherein a portion of the second dielectric material contacts the first portion of the first dielectric material, wherein a structure among the first structures includes a first conductive material contacting a substrate of the apparatus, a second conductive material formed over the first conductive material, the second conductive material being separated from the substrate by the first conductive material, and a third dielectric material formed over and contacting the second conductive material, wherein the second dielectric material contacts the third dielectric material.

2 . The apparatus of claim 1 , wherein:

the first dielectric material includes silicon dioxide; and

the second dielectric material includes silicon nitride.

3 . The apparatus of claim 1 ,

wherein one of the data lines includes part of the second conductive material.

4 . The apparatus of claim 3 , wherein:

the first conductive material includes polysilicon; and

the second conductive material includes metal.

5 . The apparatus of claim 3 , wherein the structure among the first structures includes a first dielectric structure formed on a first side of the first conductive material and a first side of the second conductive material, and a second dielectric structure formed a second side of the first conductive material, and a second side of the second conductive material, and wherein:

the first dielectric structure contacts the first side of the first conductive material and the first side of the second conductive material; and

the second dielectric structure contacts the second side of the first conductive material and the second side of the second conductive material.

6 . The apparatus of claim 1 , wherein each of the second structures includes:

a dielectric material formed over a substrate of the apparatus,

a first conductive material formed over the dielectric material;

a second conductive material formed over the first conductive material; and

a third conductive material formed over the second conductive material.

7 . The apparatus of claim 6 , wherein:

the first conductive material includes metal;

the second conductive material includes polysilicon; and

the third conductive material includes metal.

8 . The apparatus of claim 1 , wherein the apparatus comprises a memory device, the first region includes a memory array region of the memory device, and the second region includes a peripheral region of the memory device.

9 . The apparatus of claim 1 , wherein the memory element includes a capacitor.

10 . A memory device comprising:

data lines;

first structures located in a memory array region of the memory device, the first structures electrically separated from each other and including first conductive contacts coupled to the data lines;

second conductive contacts located in the memory array region of the memory device and coupled to memory elements of the memory device;

second structures located in a peripheral region of the memory device, the second structures electrically separated from each other and including respective gates of transistors in the memory array region of the memory device;

a first dielectric material formed in the peripheral region of the memory device, the first dielectric material including a first portion and a second portion, the first portion formed at a first side of a structure among the second structures, the second portion formed at a second side first of the structure; and

a second dielectric material formed over the first structures and the second structures, wherein a portion of the second dielectric material contacts the first portion of the first dielectric material, wherein a structure among the first structures includes a first conductive material contacting a substrate of the apparatus, a second conductive material formed over the first conductive material, the second conductive material being separated from the substrate by the first conductive material, and a third dielectric material formed over and contacting the second conductive material, wherein the second dielectric material contacts the third dielectric material.

11 . The apparatus of claim 10 , wherein:

the first dielectric material includes silicon dioxide; and

the second dielectric material includes silicon nitride.

12 . The apparatus of claim 10 ,

wherein one of the data lines includes part of the second conductive material.

13 . The apparatus of claim 12 , wherein:

the first conductive material includes polysilicon; and

the second conductive material includes metal.

14 . The apparatus of claim 12 , wherein the structure among the first structures includes a first dielectric structure formed on a first side of the first conductive material and a first side of the second conductive material, and a second dielectric structure formed a second side of the first conductive material, and a second side of the second conductive material, and wherein:

the first dielectric structure contacts the first side of the first conductive material and the first side of the second conductive material; and

the second dielectric structure contacts the second side of the first conductive material and the second side of the second conductive material.

15 . The apparatus of claim 10 , wherein each of the second structures includes:

a dielectric material formed over a substrate of the apparatus,

a first conductive material formed over the dielectric material;

a second conductive material formed over the first conductive material; and

a third conductive material formed over the second conductive material.

16 . The apparatus of claim 15 , wherein:

the first conductive material includes metal;

the second conductive material includes polysilicon; and

the third conductive material includes metal.

17 . The apparatus of claim 10 , wherein the memory element includes a capacitor.