Integrated circuit device, memory device, and method of manufacturing

1 . An integrated circuit (IC) device, comprising:

a substrate;

a bottom semiconductor device over the substrate; and

a top semiconductor device over the bottom semiconductor device in a thickness direction of the substrate,

wherein

the top semiconductor device and the bottom semiconductor device are of a same conductivity type, and

at least one of

a gate of the top semiconductor device is electrically coupled to a gate of the bottom semiconductor device, or

at least one source/drain of the top semiconductor device is electrically coupled to at least one source/drain of the bottom semiconductor device.

2 . The IC device of claim 1 , wherein

the gate of the top semiconductor device is electrically coupled to the gate of the bottom semiconductor device, and overlaps the gate of the bottom semiconductor device along the thickness direction.

3 . The IC device of claim 1 , wherein

a first source/drain of the top semiconductor device is electrically coupled to a first source/drain of the bottom semiconductor device, and overlaps the first source/drain of the bottom semiconductor device along the thickness direction.

4 . The IC device of claim 3 , wherein

a second source/drain of the top semiconductor device is electrically coupled to a second source/drain of the bottom semiconductor device, and overlaps the second source/drain of the bottom semiconductor device along the thickness direction.

5 . The IC device of claim 1 , further comprising:

a gate-all-around (GAA) structure configuring both the gate of the top semiconductor device and the gate of the bottom semiconductor device.

6 . The IC device of claim 1 , further comprising:

a data storage element, wherein

the top semiconductor device and the bottom semiconductor device are electrically coupled to each other to configure an access transistor, and

the access transistor is electrically coupled in series with the data storage element.

7 . The IC device of claim 1 , wherein

the gate of the top semiconductor device is electrically coupled to the gate of the bottom semiconductor device, and

the at least one source/drain of the top semiconductor device is electrically coupled to the at least one source/drain of the bottom semiconductor device.

8 . The IC device of claim 1 , wherein

both the top semiconductor device and the bottom semiconductor device are N-type transistors.

9 . The IC device of claim 1 , wherein

both the top semiconductor device and the bottom semiconductor device are P-type transistors.

10 . The IC device of claim 1 , wherein

the gate of the top semiconductor device overlap the gate of the bottom semiconductor device along the thickness direction, and

source/drains of the top semiconductor device correspondingly overlap source/drains of the bottom semiconductor device along the thickness direction.

11 . A memory device, comprising:

a bit line;

a word line;

a data storage element; and

a word line select circuit comprising:

a bottom semiconductor device; and

a top semiconductor device physically stacked on the bottom semiconductor device, wherein

the word line is electrically coupled to a gate of the top semiconductor device and a gate of the bottom semiconductor device, and

the word line select circuit and the data storage element are electrically coupled in series to the bit line.

12 . The memory device of claim 11 , wherein

the top semiconductor device and the bottom semiconductor device are electrically coupled in series to configure the word line select circuit.

13 . The memory device of claim 11 , wherein

the top semiconductor device and the bottom semiconductor device are electrically coupled in parallel to configure the word line select circuit.

14 . The memory device of claim 11 , wherein

the data storage element comprises a resistive data storage element.

15 . The memory device of claim 11 , wherein

the data storage element comprises a metal fuse.

16 . The memory device of claim 11 , further comprising:

a power switch; and

a bit line select circuit, wherein

the power switch and the bit line select circuit are electrically coupled in series between the bit line and a first node of a first power supply voltage, and

at least one of the power switch or the bit line select circuit comprises:

a further bottom semiconductor device, and

a further top semiconductor device physically stacked on the further bottom semiconductor device, and electrically coupled in series to the further bottom semiconductor device.

17 . The memory device of claim 16 , wherein

the top semiconductor device and the bottom semiconductor device are of a first conductivity type, and

the further top semiconductor device and the further bottom semiconductor device are of a second conductivity type different from the first conductivity type.

18 . The memory device of claim 16 , wherein

the word line select circuit and the data storage element are electrically coupled in series between the bit line and a second node of a second power supply voltage different from the first power supply voltage.

19 . A method of manufacturing an integrated circuit (IC) device, the method comprising:

forming a stack of semiconductor layers over a substrate;

forming first and second bottom epitaxy structures correspondingly on opposite first and second sides of the stack of semiconductor layers;

forming an isolation structure over the first and second bottom epitaxy structures;

forming first and second top epitaxy structures over the isolation structure, the first and second top epitaxy structures having a same conductivity type as the first and second bottom epitaxy structures; and

forming a first local interconnect electrically coupling the first top epitaxy structure to the first bottom epitaxy structure.

20 . The method of claim 19 , further comprising:

forming a second local interconnect electrically coupling the second top epitaxy structure to the second bottom epitaxy structure.