3D memory device, measurement method thereof, and film measurement device
A three-dimensional (3D) memory device includes a stack structure including a first stack structure and a second stack structure over the first stack structure, and a barrier layer disposed in a first channel hole in the first stack structure.
1 . A three-dimensional (3D) memory device, comprising:
a substrate;
a stack structure disposed over the substrate and comprising a first stack structure and a second stack structure over the first stack structure; and
a barrier layer disposed in each of first channel holes of the first stack structure, wherein:
the barrier layer is configured to block a signal within a wavelength range from entering the first stack structure, and a thickness of the second stack structure corresponds to a reflected portion of the signal that is reflected from the second stack structure; and
an incident angle of the signal is determined by a spacing between two adjacent barrier layers.
2 . The 3D memory device of claim 1 , wherein
the stack structure is located over the substrate, and the barrier layer corresponds to the first stack structure without extending into the substrate.
3 . The 3D memory device of claim 1 , wherein the wavelength range is within 190 nm to 700 nm.
4 . The 3D memory device of claim 1 , further comprising:
a second channel hole disposed in the second stack structure, wherein the second channel hole extends into the barrier layer in one of the first channel holes.
5 . The 3D memory device of claim 1 , wherein the barrier layer penetrates through the first stack structure.
6 . The 3D memory device of claim 1 , wherein the barrier layer is a sacrificial layer remaining after a front-end process.
7 . The 3D memory device of claim 6 , wherein a material of the sacrificial layer comprises at least one of polycrystalline silicon or carbon.
8 . The 3D memory device of claim 1 , further comprising:
a second channel hole disposed in the second stack structure, the second channel hole being staggered relative to one of the first channel holes.
9 . The 3D memory device of claim 1 , wherein the barrier layer comprises carbon.
10 . The 3D memory device of claim 1 , wherein:
the first stack structure further comprises a monitor pad disposed over the substrate.
11 . The 3D memory device of claim 1 , wherein the barrier layer is disposed on a sidewall of one of the first channel holes, without entirely extending through the first stack structure.
12 . The 3D memory device of claim 1 , wherein:
the barrier layer is a first barrier layer; and
the 3D memory device further comprises a second barrier layer disposed between the first stack structure and the second stack structure configured to block the signal from entering into the first stack structure.
13 . The 3D memory device of claim 1 , wherein:
the thickness of the second stack structure corresponds to the reflected portion of the signal that is reflected from the second stack structure having no channel hole structure.
14 . The 3D memory device of claim 1 , wherein the second stack structure has no barrier layer.
15 . The 3D memory device of claim 1 , wherein a top surface of the barrier layer is in direct contact with the second stack structure having no barrier layer.