Three-dimensional memory devices and methods for forming the same

1 . A memory device, comprising:

a conductive layer;

a stack structure comprising interleaved conductive layers and dielectric layers;

a channel structure extending through the stack structure and the conductive layer, the channel structure comprising a memory film and a semiconductor channel;

a doped semiconductor layer in contact with the semiconductor channel, wherein the conductive layer is between the doped semiconductor layer and the stack structure;

an insulating layer, wherein the doped semiconductor layer is between the insulating layer and the conductive layer; and

a source contact extending through the insulating layer and in contact with the doped semiconductor layer.

2 . The memory device of claim 1 , further comprising a contact structure extending through the doped semiconductor layer outside of the stack structure.

3 . The memory device of claim 2 , wherein the contact structure is below the conductive layer in a direction facing the stack structure.

4 . The memory device of claim 2 , further comprising a dielectric layer between the contact structure and the doped semiconductor layer.

5 . The memory device of claim 2 , further comprising a peripheral contact connected with the contact structure outside of the stack structure.

6 . The memory device of claim 1 , wherein the conductive layer comprises polysilicon, a high dielectric constant (high-k) dielectric, or a metal.

7 . The memory device of claim 1 , wherein the doped semiconductor layer comprises a plate and a plug extending from the plate into the channel structure, and the plug is in contact with the semiconductor channel.

8 . The memory device of claim 1 , wherein the memory film extends beyond the stack structure in a vertical direction and is in contact with the doped semiconductor layer.

9 . The memory device of claim 8 , wherein the semiconductor channel comprises a doped portion, and a part of the doped portion of the semiconductor channel extends in the stack structure, beyond the stack structure in the vertical direction and into the doped semiconductor layer.

10 . The memory device of claim 1 , further comprising:

a first bonding layer connected with the semiconductor channel and comprising first bonding contacts and first dielectrics isolating the first bonding contacts;

a second bonding layer comprising second bonding contacts and second dielectrics isolating the second bonding contacts; and

a peripheral circuit connected with the second bonding layer, wherein the first bonding contacts are bonded with the second bonding contacts.

11 . The memory device of claim 10 , wherein edges of the stack structure define a staircase structure facing the peripheral circuit.

12 . A memory device, comprising:

a conductive layer comprising polysilicon;

a stack structure comprising interleaved conductive layers and dielectric layers;

a channel structure extending through the stack structure and the conductive layer, the channel structure comprising a memory film and a semiconductor channel; and

a doped semiconductor layer in contact with the semiconductor channel, wherein the conductive layer is between the doped semiconductor layer and the stack structure; an insulating layer, and the doped semiconductor layer is between the insulating layer and the conductive layer;

a source contact extending through the insulating layer and in contact with the doped semiconductor layer; and

a contact structure extending through the insulating layer and the doped semiconductor layer outside of the stack structure.

13 . The memory device of claim 12 , wherein the doped semiconductor layer comprises a plate and a plug extending from the plate into the channel structure, and the plug is in contact with the semiconductor channel.

14 . The memory device of claim 12 , wherein the memory film extends beyond the stack structure in a vertical direction and is in contact with the doped semiconductor layer.

15 . The memory device of claim 14 , wherein the semiconductor channel comprises a doped portion, and a part of the doped portion of the semiconductor channel extends in the stack structure, beyond the stack structure in the vertical direction and into the doped semiconductor layer.

16 . A method for forming a memory device, comprising:

forming a conductive layer above a substrate;

forming a stack structure above the conductive layer;

forming a channel structure extending through the stack structure and the conductive layer, the channel structure comprising a memory film and a semiconductor channel;

sequentially removing the substrate and a part of the channel structure extending beyond the conductive layer to expose a part of the semiconductor channel;

forming a doped semiconductor layer in contact with the exposed part of the semiconductor channel; and

forming an insulating layer above the doped semiconductor layer.

17 . The method of claim 16 , further comprising, prior to forming the doped semiconductor layer, doping the exposed part of the semiconductor channel.

18 . The method of claim 16 , wherein forming the channel structure comprises:

forming a channel hole extending through the stack structure and the conductive layer; and

sequentially forming the memory film, the semiconductor channel, and a capping layer in the channel hole.

19 . The method of claim 16 , further comprising:

forming a source contact extending through the insulating layer and in contact with the doped semiconductor layer.

20 . The method of claim 16 , wherein the conductive layer comprises polysilicon, a high dielectric constant (high-k) dielectric, or a metal.